A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.
Adit D. SinghPublished in: DFT (2009)
Keyphrases
- cmos technology
- nm technology
- low power
- analog vlsi
- power consumption
- real time
- feature extraction
- architectural design
- management system
- software architecture
- network architecture
- circuit design
- genetic algorithm
- cloud computing
- high speed
- database
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- defect detection
- hardware architecture
- low voltage
- delay insensitive
- information systems