Kazumi Hatayama

Publication Activity (10 Years)

Years Active: 1989-2023
Publications (10 Years): 22

Top Topics

Quality Improvement

Fpga Implementation

Asynchronous Cellular Automata

Histogram Matching

Top Venues

Publications

Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. ITC (2023)
Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. IEICE Electron. Express 20 (1) (2023)
Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. ITC-Asia (2023)
Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. ATS (2022)
Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS (2022)
Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. J. Electron. Test. 38 (1) (2022)
Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
High Precision Measurement of Sub-Nano Ampere Current in ATE Environment. ATS (2021)
Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi
Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. ITC (2021)
Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi
Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. IOLTS (2021)
Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. ITC (2021)
Gaku Ogihara, Takayuki Nakatani, Daisuke Iimori, Shogo Katayama, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Jianglin Wei, Kazumi Hatayama, Haruo Kobayashi
Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production. ICECS (2021)
Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
Innovative Test Practices in Asia. VTS (2020)
Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, Kazumi Hatayama, Haruo Kobayashi
Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers. ATS (2020)
Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
Accurate Testing of Precision Voltage Reference by DC-AC Conversion. ATS (2020)
Yusuke Asada, Takahiko Shimizu, Yuji Gendai, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei, Nene Kushita, Hirotaka Arai, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi
Innovative Test Practices in Japan. VTS (2019)
Riho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
Evaluation of Null Method for Operational Amplifier Short-Time Testing. ASICON (2019)
Jiang-Lin Wei, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Nene Kushita, Takahiro Arai, Lei Sha, Anna Kuwana, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato
High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm. ASICON (2019)
Yuto Sasaki, Kosuke Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion. ITC-Asia (2019)
Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
Innovative practices on test in Japan. VTS (2018)
Kazumi Hatayama, Masahiro Ishida
Innovative practices session 10B innovative practices in Asia-2: From cost perspective. VTS (2017)
Kazumi Hatayama, Masahiro Ishida
Innovative practices session 9B innovative practices in Asia-1: From quality perspective. VTS (2017)
Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. 32 (5) (2016)
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA (2014)
Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS (2014)
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia
Special session 4B: Elevator talks. VTS (2013)
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
DART: Dependable VLSI test architecture and its implementation. ITC (2012)
Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC (2012)
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. (6) (2011)
Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Kazumi Hatayama, Tsuyoshi Shinogi
Foreword. IEICE Trans. Inf. Syst. (1) (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Scan based process parameter estimation through path-delay inequalities. ISCAS (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Path clustering for adaptive test. VTS (2010)
Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS (2009)
Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD (2009)
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium (2009)
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS (2008)
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. 3 (4) (2008)
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD (2008)
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Estimation of delay test quality and its application to test generation. ICCAD (2007)
Kazumi Hatayama
Session Abstract. VTS (2006)
Kazumi Hatayama, Rochit Rajsuman
Opportunities with the open architecture test system. ASP-DAC (2004)
Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Kazumi Hatayama, Kazuyuki Nomoto
DFT Timing Design Methodology for Logic BIST. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto
DFT timing design methodology for at-speed BIST. ASP-DAC (2003)
Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
Application of High-Quality Built-In Test to Industrial Designs. ITC (2002)
Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium (2002)
Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium (2001)
Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
Low overhead test point insertion for scan-based BIST. ITC (1999)
Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada
A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS (1997)
Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium (1997)
Michinobu Nakao, Kazumi Hatayama, Isao Higashi
Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium (1997)
Hiroshi Date, Michinobu Nakao, Kazumi Hatayama
A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium (1995)
Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi
Sequential circuit test generation by real number simulation. Systems and Computers in Japan 24 (9) (1993)
Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
Sequential Test Generation Based on Real-Value Logic. ITC (1992)
Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC (1989)