Michihiro Shintani

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 45

Top Topics

Gaussian Process

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michihiro Shintani
Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (8) (2024)
Yuta Shintani, Michiko Inoue, Michihiro Shintani
Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process. DATE (2024)
Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (1) (2024)
Yuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani
EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing. DATE (2024)
Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani
Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. ITC (2023)
Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. ASP-DAC (2023)
Ayano Takaya, Michihiro Shintani
Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning Technique. ITC-Asia (2023)
Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Yuya Isaka, Michihiro Shintani, Foisal Ahmed, Michiko Inoue
Systematic Unsupervised Recycled Field-Programmable Gate Array Detection. CoRR (2022)
Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Michihiro Shintani
Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data. ITC (2022)
Kyohei Shimozato, Michihiro Shintani, Takashi Sato
Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. CoRR (2022)
Michihiro Shintani, Mamoru Ishizaka, Michiko Inoue
Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network. ATS (2021)
Michihiro Shintani, Aoi Ueda, Takashi Sato
Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. CoRR (2021)
Foisal Ahmed, Michihiro Shintani, Michiko Inoue
Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. CoRR (2021)
Foisal Ahmed, Michihiro Shintani, Michiko Inoue
Study on High-Accuracy and Low-Cost Recycled FPGA Detection. ITC (2021)
Yuya Isaka, Foisal Ahmed, Michihiro Shintani, Michiko Inoue
Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation. IOLTS (2021)
Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue
Hardware-Software Co-Design for Decimal Multiplication. Comput. 10 (2) (2021)
Michihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. ITC (2021)
Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. CoRR (2020)
Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue
Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit. J. Electron. Test. 36 (4) (2020)
Yohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato
Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. ATS (2020)
Foisal Ahmed, Michihiro Shintani, Michiko Inoue
Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Michihiro Shintani, Tomoki Mino, Michiko Inoue
LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement. ATS (2020)
Aoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato
Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. ATS (2020)
Foisal Ahmed, Michihiro Shintani, Michiko Inoue
Low Cost Recycled FPGA Detection Using Virtual Probe Technique. ITC-Asia (2019)
Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. SoCC (2019)
Foisal Ahmed, Michihiro Shintani, Michiko Inoue
Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling. ETS (2019)
Fakir Sharif Hossain, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
Variation-Aware Hardware Trojan Detection through Power Side-channel. ITC (2018)
Michihiro Shintani, Michiko Inoue, Yoshiyuki Nakamura
Artificial Neural Network Based Test Escape Screening Using Generative Model. ITC (2018)
Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue
Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage. ATS (2018)
Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED (2018)
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC (2018)
Mian Riaz-ul-haque, Michihiro Shintani, Michiko Inoue
Decimal Multiplication Using Combination of Software and Hardware. APCCAS (2018)
Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC (2017)
Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS (2017)
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED (2017)
Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC (2017)
Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI (2016)
Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS (2016)
Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. 32 (5) (2016)
Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato
Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED (2016)
Michihiro Shintani, Takashi Sato
testing. ICCAD (2014)
Michihiro Shintani, Takashi Sato
IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. IEICE Trans. Inf. Syst. (8) (2014)
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Michihiro Shintani, Takashi Sato
Device-Parameter Estimation through IDDQ Signatures. IEICE Trans. Inf. Syst. (2) (2013)
Michihiro Shintani, Takashi Sato
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ASP-DAC (2013)
Michihiro Shintani, Takashi Sato
A Bayesian-based process parameter estimation using IDDQ current signature. VTS (2012)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Scan based process parameter estimation through path-delay inequalities. ISCAS (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Path clustering for adaptive test. VTS (2010)
Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS (2009)
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium (2009)
Hideyuki Ichihara, Toshihiro Ohara, Michihiro Shintani, Tomoo Inoue
A Variable-Length Coding Adjustable for Compressed Test Application. IEICE Trans. Inf. Syst. (8) (2007)
Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
An Adaptive Decompressor for Test Application with Variable-Length Coding. Inf. Media Technol. 1 (2) (2006)
Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue
Huffman-Based Test Response Coding. IEICE Trans. Inf. Syst. (1) (2005)
Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue
A Huffman-based coding with efficient test application. ASP-DAC (2005)
Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
A Test Decompression Scheme for Variable-Length Coding. Asian Test Symposium (2004)
Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue
Test Response Compression Based on Huffman Coding. Asian Test Symposium (2003)