Kazuhiko Iwasaki

Publication Activity (10 Years)

Years Active: 1986-2018
Publications (10 Years): 5

Top Topics

Mutation Testing

Quality Assurance

Design Automation

Test Generation

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki
Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki
Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation. ITC (2017)
Masayuki Arai, Kazuhiko Iwasaki
Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Shingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki
Critical-Area-Aware Test Pattern Generation and Reordering. ATS (2016)
Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki
Note on Fast Bridge Fault Test Generation Based on Critical Area. ICA3PP (3) (2015)
Ryo Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints. IEICE Trans. Inf. Syst. (1) (2013)
Hongbo Shi, Kazuhiko Iwasaki
Classification of DNS Queries for Anomaly Detection. PRDC (2013)
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki
Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage. Asian Test Symposium (2012)
Masayuki Arai, Kazuhiko Iwasaki
Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors. PRDC (2011)
Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. (1) (2010)
Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
Reduction of Area per Good Die for SoC Memory Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Takahiko Ikeda, Mamoru Ohara, Satoshi Fukumoto, Masayuki Arai, Kazuhiko Iwasaki
A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments. PRDC (2010)
Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS (2009)
Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5 (4) (2009)
Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Analysis of Probabilistic Trapezoid Protocol for Data Replication. J. Inf. Process. 16 (2008)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping. IEICE Trans. Inf. Syst. (3) (2008)
Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Analysis of Probabilistic Trapezoid Protocol for Data Replication. Inf. Media Technol. 3 (3) (2008)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Study on Expansion of Convolutional Compactors over Galois Field. IEICE Trans. Inf. Syst. (3) (2008)
Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
Hardware Overhead Reduction for Memory BIST. ITC (2008)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate. IEICE Trans. Inf. Syst. (3) (2008)
Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa
Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. J. Inf. Process. Syst. 4 (4) (2008)
Mamoru Ohara, Ryo Suzuki, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2006)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Expansion of Convolutional Compactors over Galois Field. ATS (2006)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Extension of coefficients for (n, k, m) convolutional-code-based packet loss recovery. Comput. Math. Appl. 51 (2) (2006)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
Test Data Compression of 100x for Scan-Based BIST. ITC (2006)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Analysis of error-masking and X-masking probabilities for convolutional compactors. ITC (2005)
Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Analysis of Probabilistic Trapezoid Protocol for Data Replication. DSN (2005)
Masayuki Arai, Tabito Suzuki, Mamoru Ohara, Satoshi Fukumoto, Kazuhiko Iwasaki, Hee Yong Youn
Analysis of Read and Write Availability for Generalized Hybrid Data Replication Protocol. PRDC (2004)
Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits. IEICE Trans. Inf. Syst. (3) (2004)
Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki
Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. Asian Test Symposium (2004)
Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Finding a Recovery Line in Uncoordinated Checkpointing. ICDCS Workshops (2004)
Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. (9) (2004)
Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
Seed Selection Procedure for LFSR-Based Random Pattern Generators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
A seed selection procedure for LFSR-based random pattern generators. ASP-DAC (2003)
Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. Asian Test Symposium (2003)
Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara
BIST-oriented test pattern generator for detection of transition faults. Systems and Computers in Japan 34 (3) (2003)
Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki
Adaptive Checkpointing for Time Warp Technique with a Limited Number of Checkpoints. ICDCS Workshops (2002)
Masayuki Arai, Hitoshi Kurosu, Mamoru Ohara, Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki
Experiment for High-Assurance Video Conference System over the Internet. HASE (2002)
Masayuki Arai, Hitoshi Kurosu, Satoshi Fukumoto, Kazuhiko Iwasaki
Evaluation of Convolutional-Code-Based FEC under Limited Recovery Time and Its Application to Real-time Transmission. PRDC (2002)
Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara
Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium (2001)
Masayuki Arai, Anna Yamamoto, Anna Yamaguchi, Satoshi Fukumoto, Kazuhiko Iwasaki
Analysis of Using Convolutional Codes to Recover Packet Losses over Burst Erasure Channels. PRDC (2001)
Takeshi Asakawa, Kazuhiko Iwasaki
Using ATPG vectors for BIST test pattern generator. Systems and Computers in Japan 32 (11) (2001)
Masayuki Arai, Anna Yamaguchi, Kazuhiko Iwasaki
Method to Recover Internet Packet Losses Using (n, n - 1, m) Convolutional Codes. DSN (2000)
Anna Yamaguchi, Masayuki Arai, Kazuhiko Iwasaki
Evaluation of multicast error recovery using convolutional codes. PRDC (2000)
Masayuki Arai, Atsushi Chiba, Kazuhiko Iwasaki
Measurement and Modeling of Burst Packet Losses in Internet End-to-End Communications. PRDC (1999)
Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki
Experimental fault analysis of 1 Mb SRAM chips. VTS (1997)
Kazuhiko Iwasaki, Shigeo Nakamura
Aliasing Error for a Mask ROM Built-In Self-Test. IEEE Trans. Computers 45 (3) (1996)
Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki
On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers. IEEE Trans. Computers 44 (11) (1995)
Kazuhiko Iwasaki, Akinori Furuta, Shigeo Nakamura
Aliasing error for a mask ROM built-in self-test. VTS (1994)
Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie
A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability. IEEE Trans. Parallel Distributed Syst. 5 (11) (1994)
Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki
On the maximum value of aliasing probabilities for single input signature registers. VTS (1993)
Masakatu Morii, Kazuhiko Iwasaki
A Note on Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 42 (9) (1993)
Kazuhiko Iwasaki, Christian Iseli, Yuji Sato
A uniform network for VLSI massively parallel computers. Systems and Computers in Japan 24 (9) (1993)
Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie
Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers. Parallel Comput. 18 (10) (1992)
Kazuhiko Iwasaki, Toru Fujiwara, Tadao Kasami
A defect-tolerant design for mask ROMs. VTS (1992)
Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie
A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability. ITC (1991)
Kazuhiko Iwasaki
Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing. Systems and Computers in Japan 21 (5) (1990)
Kazuhiko Iwasaki, Fumio Arakawa
-ary symmetric channel. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (4) (1990)
Kazuhiko Iwasaki, Noboru Yamaguchi
Design of signature circuits based on weight distributions of error-correcting codes. ITC (1990)
Kazuhiko Iwasaki, Tadahiko Nishimukai
Aliasing Probabilities and Weight Distributions of Several Codes. Systems and Computers in Japan 20 (9) (1989)
Kazuhiko Iwasaki
Analysis and proposal of signature circuits for LSI testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (1) (1988)
Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada
Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. ICCD (1988)
Kazuhiko Iwasaki, Tsuneo Funabashi, Tatsuaki Ueno
Decoding method for shortened fire codes and its application to VLSI processor. Systems and Computers in Japan 18 (1) (1987)
Kazuhiko Iwasaki, Noboru Yamaguchi, Yoshimune Hagiwara
Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit. Systems and Computers in Japan 17 (6) (1986)