Masahiro Takakura

Publication Activity (10 Years)

Years Active: 1989-2012
Publications (10 Years): 0

Top Topics

Power Consumption

Artificial Intelligence

Top Venues

Asian Test Symposium

Publications

Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium (2012)
Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium (2011)
Jun Matsushima, Yoichi Maeda, Masahiro Takakura
CooLBIST: An Effective Approach of Test Power Reduction for LBIST. ATS (2008)
Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. (9) (2004)
Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura
A Persistent Diagnostic Technique for Unstable Defects. ITC (2002)
Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato
An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium (2001)
Kohtaro Fujimoto, Satoru Kyo, Masahiro Takakura, Taro Kanaya, Yasuhide Kitagawa, Hideaki Itoh, Morinobu Takahashi, Masaki Inoue
Identification and characterization of negative regulatory elements of the human telomerase catalytic subunit (hTERT) gene promoter: possible role of MZF-2 in transcriptional repression of hTERT. Nucleic Acids Res. 28 (13) (2000)
Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium (1997)
Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. ICCAD (1991)
Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC (1989)