Hiroyuki Iwata

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 10

Top Topics

Elman Neural Network

Reduction Method

Tennessee Eastman

Fault Detection

Top Venues

IEICE Trans. Inf. Syst.

Publications

Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. 28 (3) (2023)
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. ITC (2023)
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs. ATS (2021)
Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. (11) (2020)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test 35 (3) (2018)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS (2018)
Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS (2018)
Jongseung Lee, Nobutaka Mukae, Jumpei Arata, Hiroyuki Iwata, Keiji Iramina, Koji Iihara, Makoto Hashizume
A multichannel-near-infrared-spectroscopy-triggered robotic hand rehabilitation system for stroke patients. ICORR (2017)
Hiroyuki Iwata, Jun Matsushima
Multi-configuration Scan Structure for Various Purposes. ATS (2016)
Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS (2016)
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium (2012)
Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium (2011)
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
A DFT Method for Time Expansion Model at Register Transfer Level. DAC (2007)
Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium (2005)