Hideo Fujiwara

Publication Activity (10 Years)

Years Active: 1974-2020
Publications (10 Years): 12

Top Venues

IEICE Trans. Inf. Syst.

VLSI-SoC

ETS

J. Electron. Test.

Publications

Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa
Universal Testing for Linear Feed-Forward/Feedback Shift Registers. IEICE Trans. Inf. Syst. (5) (2020)
Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara
A Test Generation Method Based on k-Cycle Testing for Finite State Machines. IOLTS (2019)
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. ACM Trans. Design Autom. Electr. Syst. 23 (6) (2018)
Hideo Fujiwara, Katsuya Fujiwara
Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents. IEICE Trans. Inf. Syst. (9) (2017)
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara
A unified test and fault-tolerant multicast solution for network-on-chip designs. ITC (2016)
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip. IEEE Trans. Computers 65 (9) (2016)
Hideo Fujiwara, Katsuya Fujiwara
Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design. IEICE Trans. Inf. Syst. (8) (2016)
Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
A scheduling method for hierarchical testability based on test environment generation results. ETS (2016)
Hideo Fujiwara, Katsuya Fujiwara
Properties of Generalized Feedback Shift Registers for Secure Scan Design. IEICE Trans. Inf. Syst. (4) (2016)
Hideo Fujiwara, Katsuya Fujiwara
Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers. IEICE Trans. Inf. Syst. (10) (2015)
Debesh Kumar Das, Hideo Fujiwara
One More Class of Sequential Circuits having Combinational Test Generation Complexity. J. Electron. Test. 31 (3) (2015)
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. ATS (2015)
Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto
Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Katsuya Fujiwara, Hideo Fujiwara
Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design. IEICE Trans. Inf. Syst. (5) (2013)
Dong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara
Thermal-aware test scheduling for NOC-based 3D integrated circuits. VLSI-SoC (2013)
Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28 (4) (2012)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara
Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. (12) (2012)
Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto
Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design. IEICE Trans. Inf. Syst. (7) (2011)
Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
Temperature-Variation-Aware Test Pattern Optimization. ETS (2011)
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
F-Scan: A DFT Method for Functional Scan at RTL. IEICE Trans. Inf. Syst. (1) (2011)
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. 27 (2) (2011)
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. ETS (2011)
Chia Yee Ooi, Hideo Fujiwara
A New Design-for-Testability Method Based on Thru-Testability. J. Electron. Test. 27 (5) (2011)
Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS (2011)
Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto
Secure scan design using shift register equivalents against differential behavior attack. ASP-DAC (2011)
Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara
Faster-than-at-speed test for increased test quality and in-field reliability. ITC (2011)
Hideo Fujiwara, Marie Engelene J. Obien
Secure and testable scan design using extended de Bruijn graphs. ASP-DAC (2010)
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
Test pattern selection to optimize delay test quality with a limited size of test set. ETS (2010)
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
On Minimization of Test Application Time for RAS. VLSI Design (2010)
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA (2010)
Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS (2010)
Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS (2010)
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. (6) (2010)
Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
Constrained ATPG for functional RTL circuits using F-Scan. ITC (2010)
Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. DDECS (2010)
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI (2010)
Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. ITC (2010)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS (2010)
Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. J. Electron. Test. 26 (2) (2010)
Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
A synthesis method to propagate false path information from RTL to gate level. DDECS (2010)
Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium (2010)
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. ETS (2010)
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. (7) (2010)
Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. IEICE Trans. Inf. Syst. (1) (2010)
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium (2010)
Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium (2010)
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS (2009)
Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara
RTL DFT techniques to enhance defect coverage for functional test sequences. HLDVT (2009)
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC (2009)
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC (2009)
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
Partial Scan Approach for Secret Information Protection. ETS (2009)
Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara
Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC (2009)
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. (10) (2008)
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Trans. Inf. Syst. (3) (2008)
Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara
Localized random access scan: Towards low area and routing overhead. ASP-DAC (2008)
Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (6) (2008)
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. (3) (2008)
Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko
Untestable Fault Identification in Sequential Circuits Using Model-Checking. ATS (2008)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Trans. Inf. Syst. (7) (2008)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Trans. Inf. Syst. (7) (2008)
Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Trans. Inf. Syst. (3) (2008)
Tomokazu Yoneda, Hideo Fujiwara
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE (2008)
Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS (2008)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. (3) (2008)
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. ATS (2008)
Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. (1) (2007)
Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE (2007)
Dong Xiang, Kaiwei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman, Jiaguang Sun
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture. IEEE Trans. Circuits Syst. II Express Briefs (5) (2007)
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD (2007)
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
TAM Design and Optimization for Transparency-Based SoC Test. VTS (2007)
Dong Xiang, Mingjing Chen, Hideo Fujiwara
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56 (12) (2007)
Dan Zhao, Unni Chandran, Hideo Fujiwara
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. ASP-DAC (2007)
Ilia Polian, Hideo Fujiwara
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. J. Electron. Test. 23 (5) (2007)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC (2007)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. ATS (2007)
Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
A DFT Method for Time Expansion Model at Register Transfer Level. DAC (2007)
Dan Zhao, Ronghua Huang, Hideo Fujiwara
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE. ATS (2007)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS (2007)
Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara
Test Scheduling for Memory Cores with Built-In Self-Repair. ATS (2007)
Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS (2007)
Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. ATS (2007)
Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara
Fault-dependent/independent Test Generation Methods for State Observable FSMs. ATS (2007)
Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. ATS (2007)
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS (2007)
Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara
Fast and effective fault simulation for path delay faults based on selected testable paths. ITC (2007)
Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. IEEE Trans. Computers 56 (4) (2007)
Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
-Notation. IEICE Trans. Inf. Syst. (8) (2007)
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. IEEE Trans. Very Large Scale Integr. Syst. 15 (7) (2007)
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS (2007)
Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT (2006)
Chia Yee Ooi, Hideo Fujiwara
A New Scan Design Technique Based on Pre-Synthesis Thru Functions. ATS (2006)
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Trans. Inf. Syst. (4) (2006)
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Trans. Inf. Syst. (3) (2006)
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
BIST Pretest of ICs: Risks and Benefits. VTS (2006)
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. ATS (2006)
Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA (2006)
Ilia Polian, Hideo Fujiwara
Functional constraints vs. test compression in scan-based delay testing. DATE (2006)
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
Power-constrained test scheduling for multi-clock domain SoCs. DATE (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hideo Fujiwara