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Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents.
Katsuya Fujiwara
Hideo Fujiwara
Hideo Tamamoto
Published in:
IPSJ Trans. Syst. LSI Des. Methodol. (2013)
Keyphrases
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shift register
design process
computer aided
database
neural network
machine learning
information systems
high speed
design principles
hardware implementation