Debesh Kumar Das

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 28

Top Topics

Genetic Algorithm

Top Venues

J. Circuits Syst. Comput.

IET Comput. Digit. Tech.

Publications

Asfak Ali, Ram Sarkar, Debesh Kumar Das
IRUVD: a new still-image based dataset for automatic vehicle detection. Multim. Tools Appl. 83 (3) (2024)
Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das
Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. VLSID (2024)
Joyati Mondal, Debesh Kumar Das, Bhargab B. Bhattacharya
Design-for-testability for reversible logic circuits based on bit-swapping. IET Quantum Commun. 5 (2) (2024)
Joyati Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das, Bhargab B. Bhattacharya
DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. J. Circuits Syst. Comput. 31 (10) (2022)
Subrata Das, Debesh Kumar Das, Soumya Pandit
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. VDAT (2022)
Joyati Mondal, Debesh Kumar Das
A new online testing technique for reversible circuits. IET Quantum Commun. 3 (1) (2022)
Tanusree Kaibartta, G. P. Biswas, Arup Kumar Pal, Debesh Kumar Das
A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC. IEEE Access 9 (2021)
Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das
Minimization of Switching Activity of Graphene Based Circuits. VLSI Design (2021)
Arindam Banerjee, Debesh Kumar Das
A Novel ALU Circuit based on Reversible Logic. J. Circuits Syst. Comput. 29 (11) (2020)
Tanusree Kaibartta, G. P. Biswas, Debesh Kumar Das
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs. J. Electron. Test. 36 (2) (2020)
Joyati Mondal, Debesh Kumar Das
An Improved Online Testing Technique For Reversible Circuits. ISDCS (2020)
Subrata Das, Debesh Kumar Das, Soumya Pandit
A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. ACM J. Emerg. Technol. Comput. Syst. 16 (3) (2020)
Arindam Banerjee, Debesh Kumar Das
Arithmetic Circuits Using Reversible Logic: A Survey Report. ACSS (1) (2019)
Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh Kumar Das
Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. J. Circuits Syst. Comput. 28 (12) (2019)
Tanusree Kaibartta, Chandan Giri, Hafizur Rahaman, Debesh Kumar Das
Approach of genetic algorithm for power-aware testing of 3D IC. IET Comput. Digit. Tech. 13 (5) (2019)
Tanusree Kaibartta, Debesh Kumar Das
Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach. VDAT (2018)
Subrata Das, Debesh Kumar Das
Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. ISVLSI (2018)
Joyati Mondal, Debesh Kumar Das
Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing. ATS (2017)
Subrata Das, Debesh Kumar Das
A technique to construct global routing trees for graphene nanoribbon (GNR). ISQED (2017)
Arindam Banerjee, Debesh Kumar Das
A new ALU architecture design using reversible logic. ISED (2016)
Arindam Banerjee, Debesh Kumar Das
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. VLSI Design (2016)
Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das
A rule-based approach for minimizing power dissipation of digital circuits. DDECS (2016)
Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. VDAT (2016)
Subrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das
Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees. ACM Great Lakes Symposium on VLSI (2016)
Arindam Banerjee, Debesh Kumar Das
A New Squarer design with reduced area and delay. IET Comput. Digit. Tech. 10 (5) (2016)
Arindam Banerjee, Debesh Kumar Das
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. J. Low Power Electron. 11 (4) (2015)
Debesh Kumar Das, Hideo Fujiwara
One More Class of Sequential Circuits having Combinational Test Generation Complexity. J. Electron. Test. 31 (3) (2015)
Arindam Banerjee, Debesh Kumar Das
Squarer design with reduced area and delay. VDAT (2015)
Arighna Deb, Debesh Kumar Das
A regular network of symmetric functions in quantum-dot cellular automata. VDAT (2014)
Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. J. Low Power Electron. 10 (3) (2014)
Bappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman
Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. ATS (2014)
Arindam Banerjee, Debesh Kumar Das
Squaring in reversible logic using iterative structure. EWDTS (2014)
Joyati Mondal, Debesh Kumar Das, Dipak Kumar Kole, Hafizur Rahaman, Bhargab B. Bhattacharya
On Designing Testable Reversible Circuits Using Gate Duplication. VDAT (2013)
Arindam Banerjee, Debesh Kumar Das
The Design of Reversible Multiplier Using Ancient Indian Mathematics. ISED (2013)
Hafizur Rahaman, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. VLSI Design (2008)
Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Asian Test Symposium (2004)
Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electron. Test. 20 (3) (2004)
Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design (2001)
Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara
Test Generation for Acyclic Sequential Circuits with Hold Registers. ICCAD (2000)
Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya
Synthesis of symmetric functions for path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (9) (2000)
Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium (1999)
Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. VLSI Design (1997)
Debesh Kumar Das, Bhargab B. Bhattacharya
Does retiming affect redundancy in sequential circuits? VLSI Design (1996)
Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya
Logical redundancies in irredundant combinational circuits. J. Electron. Test. 4 (2) (1993)