Petr Fiser

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 28

Top Topics

Power Dissipation

Functional Decomposition

Error Correction

Top Venues

Microprocess. Microsystems

Publications

Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin
On the Influence of the Laser Illumination on the Logic Cells Current Consumption. CoRR (2024)
Jan Schmidt, Petr Fiser, Miroslav Skrbek
Adaptive Input Normalization for Quantized Neural Networks. DDECS (2024)
Jan Schmidt, Petr Fiser, Miroslav Skrbek
A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks. DDECS (2024)
Subrata Das, Arighna Deb, Petr Fiser
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring. ISDCS (2023)
Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin
On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results. ICECS (2023)
Robert Hülle, Petr Fiser, Jan Schmidt
Reducing Output Response Aliasing Using Boolean Optimization Techniques. DDECS (2023)
Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. DDECS (2022)
Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola
Emerging Technologies: Challenges and Opportunities for Logic Synthesis. DDECS (2021)
Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das
Minimization of Switching Activity of Graphene Based Circuits. VLSI Design (2021)
Jaroslav Borecký, Robert Hülle, Petr Fiser
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. DSD (2020)
Jan Belohoubek, Petr Fiser, Jan Schmidt
Standard Cell Tuning Enables Data-Independent Static Power Consumption. DDECS (2020)
Martin Novotný, Petr Fiser
Special issue on DSD 2018. Microprocess. Microsystems 77 (2020)
Jan Belohoubek, Petr Fiser, Jan Schmidt
CMOS Illumination Discloses Processed Data. DSD (2019)
Jan Belohoubek, Petr Fiser, Jan Schmidt
Using Voters May Lead to Secret Leakage. DDECS (2019)
Petr Fiser, Ivo Hálecek, Jan Schmidt, Václav Simek
SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Petr Fiser, Václav Simek
Optimum polymorphic circuits synthesis method. DTIS (2018)
Robert Hülle, Petr Fiser, Jan Schmidt
ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction. Microprocess. Microsystems 61 (2018)
Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio
Synthesis of Finite State Machines on Memristor Crossbars. DDECS (2018)
Ivo Hálecek, Petr Fiser, Jan Schmidt
Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR. Microelectron. Reliab. 81 (2018)
Ivo Hálecek, Petr Fiser, Jan Schmidt
Are XORs in logic synthesis really necessary? DDECS (2017)
Petr Fiser, Ivo Hálecek, Jan Schmidt
SAT-Based Generation of Optimum Function Implementations with XOR Gates. DSD (2017)
Robert Hülle, Petr Fiser, Jan Schmidt
SAT-Based ATPG for Zero-Aliasing Compaction. DSD (2017)
Jan Belohoubek, Petr Fiser, Jan Schmidt
Error masking method based on the short-duration offline test. Microprocess. Microsystems 52 (2017)
Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser
A new user-friendly ATPG platform for digital circuits. DDECS (2016)
Jan Belohoubek, Petr Fiser, Jan Schmidt
Error Correction Method Based on the Short-Duration Offline Test. DSD (2016)
Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das
A rule-based approach for minimizing power dissipation of digital circuits. DDECS (2016)
Róbert Tamási, Miroslav Siebert, Elena Gramatová, Petr Fiser
A new method for path criticality calculation. DDECS (2016)
Jan Belohoubek, Petr Fiser, Jan Schmidt
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy. DSD (2015)
Igor Lemberski, Petr Fiser, Ruslan Suleimanov
Asynchronous sum-of-products logic minimization and orthogonalization. Int. J. Circuit Theory Appl. 42 (6) (2014)
Petr Fiser, Jan Schmidt, Jiri Balcarek
Sources of bias in EDA tools and its influence. DDECS (2014)
Jan Schmidt, Petr Fiser, Jiri Balcarek
On Robustness of EDA Tools. DSD (2014)
Jirí Balcárek, Petr Fiser, Jan Schmidt
On don't cares in test compression. Microprocess. Microsystems 38 (8) (2014)
Jiri Balcarek, Petr Fiser, Jan Schmidt
PBO-Based Test Compression. DSD (2014)
Igor Lemberski, Petr Fiser
Dual-rail asynchronous logic multi-level implementation. Integr. 47 (1) (2014)
Jiri Balcarek, Petr Fiser, Jan Schmidt
Techniques for SAT-based constrained test pattern generation. Microprocess. Microsystems 37 (2) (2013)
Jiri Balcarek, Petr Fiser, Jan Schmidt
Simulation and SAT Based ATPG for Compressed Test Generation. DSD (2013)
Jan Schmidt, Petr Fiser, Jiri Balcarek
The influence of implementation type on dependability parameters. Microprocess. Microsystems 37 (6-7) (2013)
Jan Schmidt, Petr Fiser, Jiri Balcarek
The Influence of Implementation Technology on Dependability Parameters. DSD (2012)
Petr Fiser, Jan Schmidt
Improving the iterative power of resynthesis. DDECS (2012)
Jiri Balcarek, Petr Fiser, Jan Schmidt
Techniques for SAT-Based Constrained Test Pattern Generation. DSD (2011)
Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS (2010)
Jiri Balcarek, Petr Fiser, Jan Schmidt
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. DSD (2010)
Igor Lemberski, Petr Fiser
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. DSD (2010)
Igor Lemberski, Petr Fiser
Asynchronous two-level logic of reduced cost. DDECS (2009)
Petr Fiser, David Toman
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. DSD (2009)
Jan Schmidt, Petr Fiser
The Case for a Balanced Decomposition Process. DSD (2009)
Petr Fiser, Hana Kubátová
Column-matching based mixed-mode test pattern generator design technique for BIST. Microprocess. Microsystems 32 (5-6) (2008)
Petr Fiser, Pavel Kubalík, Hana Kubátová
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. DSD (2008)
Petr Fiser, Pemysl Rucký, Irena Vanová
Fast Boolean Minimizer for Completely Specified Functions. DDECS (2008)
Petr Fiser
Pseudo-Random Pattern Generator Design for Column-Matching BIST. DSD (2007)
Petr Fiser, Hana Kubátová
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. DSD (2006)
Petr Fiser, Hana Kubátová
Multiple-Vector Column-Matching BIST Design Method. DDECS (2006)
Pavel Kubalík, Petr Fiser, Hana Kubátová
Fault Tolerant System Design Method Based on Self-Checking Circuits. IOLTS (2006)
Petr Fiser, Hana Kubátová
Survey of the Algorithms in the Column-Matching BIST Method. IOLTS (2004)
Petr Fiser, Hana Kubátová
Boolean Minimizer FC-Min: Coverage Finding Process. DSD (2004)
Petr Fiser, Jan Hlavicka, Hana Kubátová
FC-Min: A Fast Multi-Output Boolean Minimizer. DSD (2003)
Jan Hlavicka, Petr Fiser
BOOM - A Heuristic Boolean Minimizer. Comput. Artif. Intell. 22 (1) (2003)
Jan Hlavicka, Petr Fiser
Minimization and Partitioning Method Reducing Input Sets. DELTA (2002)
Jan Hlavicka, Petr Fiser
BOOM - A Heuristic Boolean Minimizer. ICCAD (2001)
Petr Fiser, Jan Hlavicka
On the Use of Mutations in Boolean Minimization. DSD (2001)