Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring.
Subrata DasArighna DebPetr FiserPublished in: ISDCS (2023)
Keyphrases
- tunnel diode
- logic circuits
- power reduction
- analog circuits
- transmission line
- digital circuits
- circuit design
- delay insensitive
- high speed
- petri net
- analog vlsi
- low power
- logic synthesis
- power consumption
- electronic circuits
- gallium arsenide
- neural network
- chip design
- genetic algorithm
- vlsi circuits
- cmos technology
- data reduction
- asynchronous circuits
- activity patterns
- reduction method
- low cost