Lukás Sekanina

ORCID

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 80

Top Venues

Publications

Jakub Husa, Lukás Sekanina
Semantic mutation operator for a fast and efficient design of bent Boolean functions. Genet. Program. Evolvable Mach. 25 (1) (2024)
Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR (2024)
Michal Pinos, Lukás Sekanina, Vojtech Mrazek
ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. CoRR (2024)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE (2024)
Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS (2024)
Michal Pinos, Vojtech Mrazek, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina
Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS (2023)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS (2023)
Marek Sedlacek, Lukás Sekanina
Evolution of Editing Scripts From Examples. GECCO Companion (2023)
Martin Hurta, Jana Schwarzerova, Thomas Nägele, Wolfram Weckwerth, Valentine Provazník, Lukás Sekanina
Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. BIBM (2023)
Tadeas Juza, Lukás Sekanina
GPAM: Genetic Programming with Associative Memory. EuroGP (2023)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR (2023)
Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina
ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE (2023)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD (2023)
Matej Valek, Lukás Sekanina
Evolutionary Approximation in Non-Local Means Image Filters. SMC (2022)
Martin Hurta, Michaela Drahosova, Lukás Sekanina, Stephen L. Smith, Jane E. Alty
Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. EuroGP (2022)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. 23 (3) (2022)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69 (2022)
Mario Barbareschi, Alberto Bosio, Lukás Sekanina, Claus Braun
Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Gener. Comput. Syst. 124 (2021)
Lukás Sekanina
Evolutionary Algorithms in Approximate Computing: A Survey. CoRR (2021)
Lukás Sekanina
Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. IEEE Access 9 (2021)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR (2021)
Michal Pinos, Vojtech Mrazek, Lukás Sekanina
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP (2021)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR (2020)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (4) (2020)
David Grochol, Lukás Sekanina
Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. CEC (2020)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC (2020)
Ting Hu, Miguel Nicolau, Lukás Sekanina
Special issue on highlights of genetic programming 2019 events. Genet. Program. Evolvable Mach. 21 (3) (2020)
Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS (2020)
Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95 (2020)
Jakub Husa, Lukás Sekanina
Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. CEC (2020)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR (2020)
Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR (2020)
Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE (2020)
Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS (2020)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR (2019)
Ondrej Koncal, Lukás Sekanina
Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. EuroGP (2019)
Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC (2019)
Filip Badan, Lukás Sekanina
Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. CoRR (2019)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD (2019)
Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR (2019)
Filip Badan, Lukás Sekanina
Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. TPNC (2019)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Circuit Approximation Method Driven by Data Distribution. CoRR (2019)
Petr Rek, Lukás Sekanina
TypeCNN: CNN Development Framework With Flexible Data Types. DATE (2019)
Michaela Drahosova, Lukás Sekanina, Michal Wiglasz
Adaptive Fitness Predictors in Coevolutionary Cartesian Genetic Programming. Evol. Comput. 27 (3) (2019)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Automated Circuit Approximation Method Driven by Data Distribution. DATE (2019)
Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. 27 (12) (2019)
Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC (2019)
Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS (2018)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
ADAC: Automated Design of Approximate Circuits. CAV (1) (2018)
Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo
Special session: How approximate computing impacts verification, test and reliability. VTS (2018)
David Grochol, Lukás Sekanina
Multi-objective Evolution of Ultra-Fast General-Purpose Hash Functions. EuroGP (2018)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS (2018)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Michal Wiglasz, Lukás Sekanina
Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. SSCI (2018)
David Grochol, Lukás Sekanina
Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. AHS (2018)
Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas
Evolving boolean functions for fast and efficient randomness testing. GECCO (2018)
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD (2017)
Michal Wiglasz, Lukás Sekanina
Evolutionary approximation of gradient orientation module in HOG-based human detection system. GlobalSIP (2017)
David Grochol, Lukás Sekanina
Multi-objective evolution of hash functions for high speed networks. CEC (2017)
Filip Kesner, Lukás Sekanina, Milan Brazdil
Modular framework for detection of inter-ictal spikes in iEEG. EMBC (2017)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Towards low power approximate DCT architecture for HEVC standard. DATE (2017)
Roland Dobai, Jan Korenek, Lukás Sekanina
Evolutionary design of hash function pairs for network filters. Appl. Soft Comput. 56 (2017)
Milos Minarik, Lukás Sekanina
On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. EuroGP (2017)
Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI (2017)
Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE (2017)
Lukás Sekanina
Introduction to approximate computing: Embedded tutorial. DDECS (2016)
Petr Dvoracek, Lukás Sekanina
Evolutionary Approximation of Edge Detection Circuits. EuroGP (2016)
Lukás Sekanina, Vlastimil Kapusta
Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. GECCO (Companion) (2016)
David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek, Vlastimil Kosar
Evolutionary circuit design for fast FPGA-based classification of network application protocols. Appl. Soft Comput. 38 (2016)
Filip Vaverka, Radek Hrbacek, Lukás Sekanina
Evolving component library for approximate high level synthesis. SSCI (2016)
Roland Dobai, Jan Korenek, Lukás Sekanina
Adaptive development of hash functions in FPGA-based network routers. SSCI (2016)
Zdenek Vasícek, Lukás Sekanina
Evolutionary design of complex approximate combinational circuits. Genet. Program. Evolvable Mach. 17 (2) (2016)
David Grochol, Lukás Sekanina
Evolutionary Design of Fast High-quality Hash Functions for Network Applications. GECCO (2016)
Antonio Sanchez-Clemente, Luis Entrena, Radek Hrbacek, Lukás Sekanina
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Trans. Reliab. 65 (4) (2016)
Zdenek Vasícek, Lukás Sekanina
Search-based synthesis of approximate circuits implemented into FPGAs. FPL (2016)
Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD (2016)
Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina
Evolutionary functional approximation of circuits implemented into FPGAs. SSCI (2016)
Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina
Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) (2015)
Zdenek Vasícek, Lukás Sekanina
Evolutionary Approach to Approximate Digital Circuits Design. IEEE Trans. Evol. Comput. 19 (3) (2015)
Roland Dobai, Lukás Sekanina
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Trans. Reconfigurable Technol. Syst. 8 (3) (2015)
David Grochol, Lukás Sekanina, Martin Zádník, Jan Korenek
A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. EvoApplications (2015)
Zdenek Vasícek, Lukás Sekanina
Evolutionary Approximation of Complex Digital Circuits. GECCO (Companion) (2015)
Michaela Sikulová, Jiri Hulva, Lukás Sekanina
Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. EuroGP (2015)
Zdenek Vasícek, Lukás Sekanina
Circuit Approximation Using Single- and Multi-objective Cartesian GP. EuroGP (2015)
Jiri Petrlik, Lukás Sekanina
Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. ITSC (2015)
Zdenek Vasícek, Lukás Sekanina
Evolutionary design of approximate multipliers under different error metrics. DDECS (2014)
Milos Minarik, Lukás Sekanina
Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. EuroGP (2014)
Michaela Sikulová, Gergely Komjathy, Lukás Sekanina
Towards compositional coevolution in evolutionary circuit design. ICES (2014)
Lukás Sekanina, Ondrej Ptak, Zdenek Vasícek
Cartesian genetic programming as local optimizer of logic networks. IEEE Congress on Evolutionary Computation (2014)
Roland Dobai, Kyrre Glette, Jim Tørresen, Lukás Sekanina
Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays. ICES (2014)
Lukás Sekanina, Zdenek Vasícek
On Evolutionary Approximation of Logic Circuits. Computing with New Resources (2014)
Jiri Petrlik, Otto Fucík, Lukás Sekanina
Multiobjective selection of input sensors for travel times forecasting using support vector regression. CIVTS (2014)
Zdenek Vasícek, Lukás Sekanina
How to evolve complex combinational circuits from scratch? ICES (2014)
Jiri Petrlik, Otto Fucík, Lukás Sekanina
Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. PPSN (2014)
Radek Hrbacek, Lukás Sekanina
Towards highly optimized cartesian genetic programming: from sequential via SIMD and thread to massive parallel implementation. GECCO (2014)
Lukás Sekanina
Ubiquity symposium: Evolutionary computation and the processes of life: evolutionary computation in physical world. Ubiquity 2013 (February) (2013)
Zdenek Vasícek, Michal Bidlo, Lukás Sekanina
Evolution of efficient real-time non-linear image filters for FPGAs. Soft Comput. 17 (11) (2013)

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Publication Activity (10 Years)

Top Topics

Top Venues

Lukás Sekanina