Witold A. Pleskacz

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 36

Top Topics

International Symposium

Phase Locked Loop

Instruction Set

Top Venues

Publications

Marika Grochowska, Witold A. Pleskacz
The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies. DDECS (2024)
Bohdan Shveida, Krzysztof Marcinek, Witold A. Pleskacz
Implementation of Hardware Trace Buffer Module for RISC-V Processor Core. MIXDES (2024)
Jakub Misztal, Mateusz Korona, Witold A. Pleskacz
Bridge Circuit Converting Atomic Transactions Between AMBA AXI4 and AMBA AXI5 Standards. MIXDES (2024)
Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz
Dual TDL Based Phase Difference Detector Architecture. MIXDES (2023)
Adam Borkowski, Krzysztof Siwiec, Witold A. Pleskacz
DC/DC Buck Converter Soft-Start Methods. MIXDES (2022)
Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz
Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits. MIXDES (2022)
Pawel Pienczuk, Witold A. Pleskacz, Mateusz Teodorowski
Class AB Operational Amplifier in CMOS 55 nm Technology. MIXDES (2021)
Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz
NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 20 (4) (2020)
Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz
CMOS Differential Amplifier as a Physically Unclonable Function. DDECS (2020)
Krzysztof Marcinek, Witold A. Pleskacz
GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing. Sensors 20 (2) (2020)
Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz
Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069. Sensors 20 (19) (2020)
Sebastian Cieslak, Adrian Oleksiak, Krzysztof Marcinek, Witold A. Pleskacz
Retargeting the MIPS-II CPU Core to the RISC-V Architecture. MIXDES (2019)
Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz
Configurable MBIST Processor for Embedded Memories Testing. MIXDES (2019)
Adam Borkowski, Tomasz Borejko, Witold A. Pleskacz
DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology. MIXDES (2019)
Lukasz Ostrowski, Krzysztof Marcinek, Witold A. Pleskacz
Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication. MIXDES (2019)
Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC (2019)
Adrian Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, Witold A. Pleskacz
Design and Verification Environment for RISC-V Processor Cores. MIXDES (2019)
Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz
Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. DDECS (2019)
Daniel Pietron, Igor Butryn, Lukasz Wiechowski, Witold A. Pleskacz
Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology. MIXDES (2018)
Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz
2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. DDECS (2018)
Zoran Stamenkovic, Ondrej Novák, Witold A. Pleskacz
Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017). Microelectron. Reliab. 81 (2018)
Igor Butryn, Lukasz Wiechowski, Daniel Pietron, Witold A. Pleskacz
Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology. MIXDES (2018)
Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz
Analog front-end for precise human body temperature measurement. DDECS (2017)
Michal Wysocki, Krzysztof Siwiec, Witold A. Pleskacz
EIA/TIA-485 transceiver in standard 130 nm CMOS technology. MIXDES (2017)
Daniel Pietron, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz
Importance of on-chip inductor modeling in radio frequency integrated circuits. MIXDES (2017)
Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz
Temperature calibration technique based on on-chip resistor. MIXDES (2017)
Arkadiusz W. Luczyk, Konrad Neneman, Witold A. Pleskacz
Principal component analysis of accelerations in human dynamic movements: A sample set length effect study. MIXDES (2017)
Igor Butryn, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz
Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology. DDECS (2016)
Cezary Kolacinski, Jerzy Wasowski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz
Dedicated chip for pulse oximetry measurements. EWDTS (2016)
Jakub Kopanski, Lukasz Wiechowski, Krzysztof Siwiec, Witold A. Pleskacz
A low sampling frequency switched capacitor low-pass filter for wireless receivers. MIXDES (2016)
Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz
Precision human body temperature measurement based on thermistor sensor. DDECS (2016)
Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
BioSoC: Highly integrated System-on-Chip for health monitoring. DDECS (2016)
Konrad Neneman, Arkadiusz W. Luczyk, Witold A. Pleskacz
Monitoring of dynamic movements using acceleration measurements. MIXDES (2016)
Cezary Kolacinski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Jerzy Wasowski, Tomasz Borejko, Krzysztof Siwiec, Witold A. Pleskacz
The integrated transmitter and receiver modules for pulse oximeter system. MIXDES (2016)
Marek Cieplucha, Witold A. Pleskacz
New architecture of the object-oriented functional coverage mechanism for digital verification. IVSW (2016)
Pawel Wiecha, Marek Cieplucha, Patryk Kloczko, Witold A. Pleskacz
Architecture and design of a Bluetooth Low Energy Controller. MIXDES (2016)
Krzysztof Marcinek, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
Implementation of the ADELITE Microcontroller for Biomedical Applications. DDECS (2015)
Maciej Moskala, Patryk Kloczko, Marek Cieplucha, Witold A. Pleskacz
UVM-based Verification of Bluetooth Low Energy Controller. DDECS (2015)
Krzysztof Siwiec, Krzysztof Marcinek, Tomasz Borejko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz
A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring. MIXDES (2015)
Mariusz Derlecki, Tomasz Borejko, Witold A. Pleskacz
IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology. MIXDES (2015)
Andrzej Grodzicki, Witold A. Pleskacz
A Low Ripple Current Mode Voltage Doubler. DDECS (2015)
Aleh Halauko, Tomasz Borejko, Witold A. Pleskacz
Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications. MIXDES (2015)
Daniel Pietron, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz
Implementation of the Bluetooth receiver RF front-end in the CMOS-RF 130 nm technology. MIXDES (2014)
Andrzej Grodzicki, Witold A. Pleskacz
Multistage low ripple charge pump. DDECS (2014)
Lukasz Wiechowski, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz
Simulink model of GFSK demodulator based on time-to-digital converter. MIXDES (2014)
Krzysztof Marcinek, Witold A. Pleskacz
ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model. Microprocess. Microsystems 37 (6-7) (2013)
Krzysztof Siwiec, Aleksander Koter, Witold A. Pleskacz
Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies. DDECS (2013)
Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
LC-VCO design automation tool for nanometer CMOS technology. DDECS (2012)
Krzysztof Marcinek, Witold A. Pleskacz
AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems. DDECS (2012)
Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. DDECS (2011)
Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz
CAD tool for PLL Design. DDECS (2011)
Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz
A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. DDECS (2011)
Jakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski
A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology. DDECS (2011)
Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. DDECS (2010)
Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. DDECS (2009)
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz
Enhanced LEON3 core for superscalar processing. DDECS (2009)
Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. DDECS (2009)
Tomasz Borejko, Witold A. Pleskacz
A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. DDECS (2008)
Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. DDECS (2008)
Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD (2008)
Andrzej Wielgus, Witold A. Pleskacz
Characterization of CMOS sequential standard cells for defect based voltage testing. EWDTS (2008)
Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz
Various MDCT implementations in 0.35µm CMOS. DDECS (2008)
Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. DDECS (2008)
Witold A. Pleskacz, Viera Stopjaková, Tomasz Borejko, Artur Jutman, Andrzej Wakanis
DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. IEEE Trans. Ind. Electron. 55 (6) (2008)
Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. DDECS (2007)
Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
Power Dissipation in Basic Global Clock Distribution Networks. DDECS (2007)
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS (2007)
Witold A. Pleskacz, Tomasz Borejko, A. Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar
DefSim: CMOS Defects on Chip for Research and Education. LATW (2006)
Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz
DOT: new deterministic defect-oriented ATPG tool. ETS (2005)
Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD (2005)
Dominik Kasprowicz, Witold A. Pleskacz
Improvement of integrated circuit testing reliability by using the defect based approach. Microelectron. Reliab. 43 (6) (2003)
T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. 42 (7) (2002)
Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz
CMOS Standard Cells Characterization for IDDQ Testing. DFT (2002)
Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED (2001)
Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz
CMOS Standard Cells Characterization for Defect Based Testing. DFT (2001)
Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectron. Reliab. 41 (12) (2001)
Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
Hierarchical defect-oriented fault simulation for digital circuits. ETW (2000)
Mykola Blyzniuk, Taras Panchak, Wieslaw Kuzmicz, Witold A. Pleskacz
Graphical user interface of FIESTA - software for faults identification and estimation of testability of VLSI circuits. CCU (2000)
Witold A. Pleskacz
Yield Estimation of VLSI Circuits with Downscaled Layouts. DFT (1999)
Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
Detection of Yield Trends. DFT (1997)
Witold A. Pleskacz, Wojciech Maly
Improved Yield Model for Submicron Domain. DFT (1997)
Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
CAD at the Design-Manufacturing Interface. DAC (1997)
Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly
Extraction of critical areas for opens in large VLSI circuits. DFT (1996)
Witold A. Pleskacz, Wieslaw Kuzmicz
SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. ED&TC (1995)