Raimund Ubar

ORCID

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 52

Top Venues

DDECS

DSD

Microprocess. Microsystems

LATW

Publications

Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI (2022)
Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. CoRR (2021)
Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD (2021)
Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
New categories of Safe Faults in a processor-based Embedded System. CoRR (2020)
Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik
Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems 77 (2020)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. 36 (1) (2020)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD (2020)
Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. IOLTS (2020)
Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS (2019)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) (2019)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR (2019)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC (2019)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS (2019)
Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
New categories of Safe Faults in a processor-based Embedded System. DDECS (2019)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
Mixed-level identification of fault redundancy in microprocessors. CoRR (2019)
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
Mixed-level identification of fault redundancy in microprocessors. LATS (2019)
Adeboye Stephen Oyeniran, Raimund Ubar
High-Level Functional Test Generation for Microprocessor Modules. MIXDES (2019)
Lembit Jürimägi, Raimund Ubar, Vladimir Viies
Equivalent Transformations of Structurally Synthesized BDDs and Applications. MECO (2019)
Raimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin
True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. DSD (2019)
Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS (2018)
Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. 81 (2018)
Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Combined pseudo-exhaustive and deterministic testing of array multipliers. AQTR (2018)
Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
Timing-critical path analysis with structurally synthesized BDDs. MECO (2018)
Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES (2018)
Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. ISCAS (2018)
Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar
Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. DDECS (2018)
Stephen Adeboye Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
High-level test generation for processing elements in many-core systems. ReCoSoC (2017)
Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
High-level test data generation for software-based self-test in microprocessors. MECO (2017)
Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein
From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS (2017)
Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Automated software-based self-test generation for microprocessors. MIXDES (2017)
Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
A scalable technique to identify true critical paths in sequential circuits. DDECS (2017)
Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies
Modeling and simulation of circuits with shared structurally synthesized BDDs. Microprocess. Microsystems 48 (2017)
Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32 (3) (2016)
Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik
A novel random approach to diagnostic test generation. NORCAS (2016)
Raimund Ubar, Stephen Adeboye Oyeniran
Multiple control fault testing in digital systems with high-level decision diagrams. AQTR (2016)
Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS (2016)
Sergei Kostin, Elmet Orasson, Raimund Ubar
A tool set for teaching design-for-testability of digital circuits. EWME (2016)
Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar
High-level modeling and testing of multiple control faults in digital systems. DDECS (2016)
Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Gate-level modelling of NBTI-induced delays under process variations. LATS (2016)
Artjom Jasnetski, Raimund Ubar, Anton Tsertov
On automatic software-based self-test program generation based on high-level decision diagrams. LATS (2016)
Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik
Scalable algorithm for structural fault collapsing in digital circuits. VLSI-SoC (2015)
Maksim Gorev, Raimund Ubar, Sergei Devadze
Fault simulation with parallel exact critical path tracing in multiple core environment. DATE (2015)
Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS (2015)
Jaak Kousaar, Raimund Ubar, Igor Aleksejev
Complex delay fault reasoning with sequential 7-valued algebra. LATS (2015)
Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. VLSI-SoC (Selected Papers) (2015)
Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS (2015)
Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems 39 (8) (2015)
Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems 39 (8) (2015)
Raimund Ubar, Stephen Adeboye Oyeniran, Mario Schölzel, Heinrich Theodor Vierhaus
Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT (2015)
Raimund Ubar, Lembit Jurimagi, Jaan Raik
Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. NORCAS (2015)
Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze
Combinational fault simulation in sequential circuits. ISCAS (2015)
Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Galina Josifovska, Stephen Adeboye Oyeniran
Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. DSD (2015)
Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
Automated Design Error Localization in RTL Designs. IEEE Des. Test 31 (1) (2014)
Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik
Software-based self-test generation for microprocessors with high-level decision diagrams. LATW (2014)
Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik, Raimund Ubar
Advanced technical education in the age of cyber physical systems. EWME (2014)
Raimund Ubar, Dmitri Mironov
Lower bounds of the size of Shared Structurally Synthesized BDDs. DDECS (2014)
Dmitri Mironov, Raimund Ubar, Jaan Raik
Logic simulation and fault collapsing with shared structurally synthesized bdds. ETS (2014)
Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. EWME (2014)
Raimund Ubar, Mihhail Marenkov, Dmitri Mironov, Vladimir Viies
Modeling sequential circuits with shared structurally synthesized BDDs. IDT (2014)
Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications (2014)
Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti
Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW (2014)
Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Critical Path Tracing Based Simulation of Transition Delay Faults. DSD (2014)
Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP (2013)
Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls
Identifying NBTI-Critical Paths in Nanoscale Logic. DSD (2013)
Raimund Ubar
Diagnostic modeling of digital systems with low- and high-level decision diagrams. LATW (2013)
Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Assessment of diagnostic test for automated bug localization. LATW (2013)
Raimund Ubar, Sergei Kostin, Jaan Raik
Synthesis of multiple fault oriented test groups from single fault test sets. DTIS (2013)
Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems 37 (4-5) (2013)
Ivo Fridolin, Deniss Karai, Sergei Kostin, Raimund Ubar
Accurate Dialysis Dose Evaluation and Extrapolation Algorithms During Online Optical Dialysis Monitoring. IEEE Trans. Biomed. Eng. 60 (5) (2013)
Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28 (4) (2012)
Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. 28 (4) (2012)
Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi
Combining dynamic slicing and mutation operators for ESL correction. ETS (2012)
Raimund Ubar, Viljar Indus, Oliver Kalmend, Teet Evartson, Elmet Orasson
Functional Built-In Self-Test for processor cores in SoC. NORCHIP (2012)
Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
Automated correction of design errors by edge redirection on High-Level Decision Diagrams. ISQED (2012)
Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW (2012)
Raimund Ubar, Sergei Kostin, Jaan Raik
Multiple stuck-at-fault detection theorem. DDECS (2012)
Raimund Ubar, Sergei Kostin, Jaan Raik
How to Prove that a Circuit is Fault-Free? DSD (2012)
Raimund Ubar, Sergei Kostin, Jaan Raik
About robustness of test patterns regarding multiple faults. LATW (2012)
Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov
Automated test bench generation for high-level synthesis flow ABELITE. EWDTS (2011)
Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT (2011)
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium (2011)
Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
Probabilistic equivalence checking based on high-level decision diagrams. DDECS (2011)
Eero Ivask, Sergei Devadze, Raimund Ubar
Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Comput. Pract. Exp. 12 (1) (2011)
Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS (2011)
Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
Mutation analysis for SystemC designs at TLM. LATW (2011)
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
SoC and Board Modeling for Processor-Centric Board Testing. DSD (2011)
Sergei Kostin, Raimund Ubar, Jaan Raik
Defect-oriented module-level fault diagnosis in digital circuits. DDECS (2011)
Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. HLDVT (2011)
Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
Fault collapsing with linear complexity in digital circuits. ISCAS (2010)
Eero Ivask, Sergei Devadze, Raimund Ubar
Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS (2010)
Yuriy A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik
Evolutionary Approach to Test Generation for Functional BIST CoRR (2010)
Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD (2010)
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova
An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS (2010)
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA (2010)
Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko
Constraint-based test pattern generation at the Register-Transfer Level. DDECS (2010)
Heinz-Dietrich Wuttke, Raimund Ubar, Karsten Henke
Remote and Virtual Laboratories in Problem-Based Learning Scenarios. ISM (2010)
Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi
Mutation analysis with high-level decision diagrams. LATW (2010)
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Parallel X-fault simulation with critical path tracing technique. DATE (2010)
Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED (2010)
Eero Ivask, Sergei Devadze, Raimund Ubar
Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Raimund Ubar