Anton Tsertov

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 11

Top Topics

Data Collection And Analysis

Test Generation

Cross Disciplinary

Top Venues

Publications

Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS (2024)
Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT (2023)
Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR (2023)
Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. ITC (2019)
Aleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. ETS (2019)
Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
High-level test data generation for software-based self-test in microprocessors. MECO (2017)
Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Automated software-based self-test generation for microprocessors. MIXDES (2017)
Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
A suite of IEEE 1687 benchmark networks. ITC (2016)
Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov
FPGA-controlled PCBA power-on self-test using processor's debug features. DDECS (2016)
Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar
High-level modeling and testing of multiple control faults in digital systems. DDECS (2016)
Artjom Jasnetski, Raimund Ubar, Anton Tsertov
On automatic software-based self-test program generation based on high-level decision diagrams. LATS (2016)
Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS (2015)
Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik
Software-based self-test generation for microprocessors with high-level decision diagrams. LATW (2014)
Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. EWME (2014)
Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski
On in-system programming of non-volatile memories. MIXDES (2013)
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium (2011)
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
SoC and Board Modeling for Processor-Centric Board Testing. DSD (2011)
Anton Tsertov, Artur Jutman, Sergei Devadze
Testing beyond the SoCs in a lego style. EWDTS (2010)
Artur Jutman, Anton Tsertov, Raimund Ubar
Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS (2008)