Sergei Devadze

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 15

Top Topics

Special Session

Fault Detection

Application Specific

Top Venues

Microprocess. Microsystems

Publications

Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS (2024)
Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT (2023)
Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR (2023)
Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman
HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. CoRR (2022)
Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran
Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS (2019)
Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS (2018)
Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES (2018)
Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure. IEEE Des. Test 34 (6) (2017)
Igor Aleksejev, Artur Jutman, Sergei Devadze
Run-time reconfigurable instruments for advanced board-level testing. IEEE Instrum. Meas. Mag. 20 (4) (2017)
Sergei Odintsov, Artur Jutman, Sergei Devadze
Marginal PCB assembly defect detection on DDR3/4 memory bus. ITC (2017)
Artur Jutman, Igor Aleksejev, Sergei Devadze
On coverage of timing related faults at board level. ETS (2016)
Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. J. Electron. Test. 32 (3) (2016)
Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
A suite of IEEE 1687 benchmark networks. ITC (2016)
Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL (2016)
Konstantin Shibin, Sergei Devadze, Artur Jutman
On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. LATS (2016)
Maksim Gorev, Raimund Ubar, Sergei Devadze
Fault simulation with parallel exact critical path tracing in multiple core environment. DATE (2015)
Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
Virtual reconfigurable scan-chains on FPGAs for optimized board test. LATS (2015)
Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems 39 (8) (2015)
Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems 39 (8) (2015)
Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze
Combinational fault simulation in sequential circuits. ISCAS (2015)
Konstantin Shibin, Sergei Devadze, Artur Jutman
Asynchronous Fault Detection in IEEE P1687 Instrument Network. NATW (2014)
Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath
Design, Verification, and Application of IEEE 1687. ATS (2014)
Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Critical Path Tracing Based Simulation of Transition Delay Faults. DSD (2014)
Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP (2013)
Artur Jutman, Sergei Devadze, Konstantin Shibin
Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. IEEE Des. Test 30 (5) (2013)
Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski
On in-system programming of non-volatile memories. MIXDES (2013)
Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel
Embedded synthetic instruments for Board-Level testing. ETS (2012)
Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel
FPGA-based synthetic instrumentation for board test. ITC (2012)
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium (2011)
Artur Jutman, Sergei Devadze, Igor Aleksejev
Invited paper: System-wide fault management based on IEEE P1687 IJTAG. ReCoSoC (2011)
Eero Ivask, Sergei Devadze, Raimund Ubar
Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Comput. Pract. Exp. 12 (1) (2011)
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
SoC and Board Modeling for Processor-Centric Board Testing. DSD (2011)
Eero Ivask, Sergei Devadze, Raimund Ubar
Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS (2010)
Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD (2010)
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA (2010)
Anton Tsertov, Artur Jutman, Sergei Devadze
Testing beyond the SoCs in a lego style. EWDTS (2010)
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Parallel X-fault simulation with critical path tracing technique. DATE (2010)
Eero Ivask, Sergei Devadze, Raimund Ubar
Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC (2010)
Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
Turning JTAG inside out for fast extended test access. LATW (2009)
Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
Fast extended test access via JTAG and FPGAs. ITC (2009)
Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA (2008)
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Parallel fault backtracing for calculation of fault coverage. ASP-DAC (2008)
Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke
Learning Digital Test and Diagnostics via Internet. Int. J. Online Eng. 3 (1) (2007)
Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS (2007)
Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar
Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW (2006)
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC (2005)