Görschwin Fey

ORCID

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 75

Top Venues

Universität Bremen (PHD)

Education History

Universität Bremen

PHD

Publications

Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Görschwin Fey
FINaL: Driving High-Level Fault Injection Campaigns with Natural Language. ETS (2023)
Markus Knitt, Swantje Plambeck, Jan Christian Wieck, Julian Kohlisch, Stephan Balduin, Eric M. S. P. Veith, Jakob Schyga, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt
Towards the Automatic Generation of Models for Prediction, Monitoring, and Testing of Cyber-Physical Systems. ETFA (2023)
Arne Grünhagen, Marina Tropmann-Frick, Annika Eichler, Görschwin Fey
Predictive Maintenance for the Optical Synchronization System of the European XFEL: A Systematic Literature Survey. BTW (2023)
Leandro Lanzieri, Gianluca Martino, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt, Matthias Wählisch
A Review of Techniques for Ageing Detection and Monitoring on Embedded Systems. CoRR (2023)
Arne Grünhagen, Maximilian Schütte, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey
Enhancing Data Acquisition and Fault Analysis for Large-Scale Facilities: A Case Study on the Laser-Based Synchronization System at the European X-Ray Free-Electron Laser. LWDA (2023)
Fin Hendrik Bahnsen, Bernhard J. Berger, Görschwin Fey
GLRP: Guided by Layer-wise Relevance Propagation - Selecting Crucial Neurons in Artificial Neural Networks. MOCAST (2023)
Hany Abdelmaksoud, Zain Alabedin Haj Hammadeh, Görschwin Fey, Daniel Lüdtke
DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation. DATE (2023)
Arne Grünhagen, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey
Data-Based Condition Monitoring and Disturbance Classification in Actively Controlled Laser Oscillators. EJC (2023)
Leandro Lanzieri, Peter Kietzmann, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt
Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. CoRR (2023)
Swantje Plambeck, Görschwin Fey
Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. DDECS (2023)
Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt
Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. IPIN (2022)
Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt
Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. CoRR (2022)
Swantje Plambeck, Görschwin Fey
Regression Trees for System Models and Prediction. OVERLAY@AI*IA (2022)
Görschwin Fey, Martin Fränzle, Rolf Drechsler
Self-Explanation in Systems of Systems. RE Workshops (2022)
Ahmad Al-Zoubi, Gianluca Martino, Fin Hendrik Bahnsen, Jun Zhu, Holger Schlarb, Görschwin Fey
CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL. SOCC (2022)
Swantje Plambeck, Görschwin Fey
Decision Tree Models of Continuous Systems. ETFA (2022)
Lutz Schammer, Jan Runge, Paula Klimach, Görschwin Fey
Design Understanding: Identifying Instruction Pipelines in Hardware Designs. MOCAST (2022)
Gianluca Martino, Görschwin Fey
Runtime Monitoring of c-LTL Specifications on FPGAs Using HLS. SMACD (2022)
Swantje Plambeck, Lutz Schammer, Görschwin Fey
On the Viability of Decision Trees for Learning Models of Systems. ASP-DAC (2022)
Arne Grünhagen, Julien Branlard, Annika Eichler, Gianluca Martino, Görschwin Fey, Marina Tropmann-Frick
Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining. ATS (2021)
Fin Hendrik Bahnsen, Görschwin Fey
YAPS - Your Open Examination System for Activating and emPowering Students. CoRR (2021)
Swantje Plambeck, Jakob Schyga, Johannes Hinckeldeyn, Jochen Kreutzfeldt, Görschwin Fey
Automata Learning for Automated Test Generation of Real Time Localization Systems. CoRR (2021)
Swantje Plambeck, Gianluca Martino, Görschwin Fey
Metrics for the Evaluation of Approximate Sequential Streaming Circuits. DSD (2021)
Gianluca Martino, Arne Grünhagen, Julien Branlard, Annika Eichler, Görschwin Fey, Holger Schlarb
Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems. DSD (2021)
Fin Hendrik Bahnsen, Jan Kaiser, Görschwin Fey
Designing Recurrent Neural Networks for Monitoring Embedded Devices. ETS (2021)
Fin Hendrik Bahnsen, Görschwin Fey
YAPS - Your Open Examination System for Activating and emPowering Students. ICCSE (2021)
Lutz Schammer, Swantje Plambeck, Fin Hendrik Bahnsen, Görschwin Fey
Learning Models of Cyber-Physical Systems using Automata Learning. COMPSAC (2021)
Fin Hendrik Bahnsen, Vanessa Klebe, Görschwin Fey
Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference. MOCAST (2021)
Gianluca Martino, Heinz Riener, Görschwin Fey
Revisiting Explicit Enumeration for Exact Synthesis. DSD (2020)
Fin Hendrik Bahnsen, Görschwin Fey
Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. DSD (2019)
Fin Hendrik Bahnsen, Görschwin Fey
Approximation of Neural Networks for Verification. MBMV (2019)
Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck
Synthesizing adaptive test strategies from temporal logic specifications. Formal Methods Syst. Des. 55 (2) (2019)
Görschwin Fey, Alberto García Ortiz
Symbolic Circuit Analysis under an Arc Based Timing Model. ETS (2019)
Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik
Engineering of an Effective Automatic Dynamic Assertion Mining Platform. VLSI-SoC (2019)
Gianluca Martino, Görschwin Fey
Syntax-Guided Enumeration of Temporal Properties. FDL (2019)
Görschwin Fey, Rolf Drechsler
Self-Explaining Digital Systems - Some Technical Steps. MBMV (2019)
Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener
. VLSI-SoC (2018)
Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck
Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. CoRR (2018)
Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey
Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS (2018)
Rolf Drechsler, Christoph Lüth, Görschwin Fey, Tim Güneysu
Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW (2018)
Abraham Temesgen Tibebu, Görschwin Fey
Augmenting All Solution SAT Solving for Circuits with Structural Information. DDECS (2018)
Jan Malburg, Heinz Riener, Görschwin Fey
Mining Latency Guarantees for RTL Designs. ISMVL (2018)
Jan Malburg, Tino Flenker, Görschwin Fey
Property mining using dynamic dependency graphs. ASP-DAC (2017)
Tino Flenker, Görschwin Fey
Mapping abstract and concrete hardware models for design understanding. DDECS (2017)
Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. J. Electron. Test. 33 (1) (2017)
Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19 (5) (2017)
Heinz Riener, Rüdiger Ehlers, Görschwin Fey
CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. ASP-DAC (2017)
Gökçe Aydos, Görschwin Fey
Empirical results on parity-based soft error detection with software-based retry. Microprocess. Microsystems 48 (2017)
Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Counterexample-Guided EF Synthesis of Boolean Functions. MBMV (2017)
Robert Schmidt, Alberto García Ortiz, Görschwin Fey
Temporal redundancy latch-based architecture for soft error mitigation. IOLTS (2017)
Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. ISVLSI (2017)
Niels Thole, Görschwin Fey, Alberto García Ortiz
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. ISVLSI (2016)
Heinz Riener, Görschwin Fey
Counterexample-guided diagnosis. IVSW (2016)
Gökçe Aydos, Görschwin Fey
Exploiting error detection latency for parity-based soft error detection. DDECS (2016)
Niels Thole, Lorena Anghel, Görschwin Fey
A hybrid algorithm to conservatively check the robustness of circuits. ETS (2016)
Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken
Multilevel design understanding: from specification to logic (invited paper). ICCAD (2016)
Jan Malburg, Alexander Finder, Görschwin Fey
Debugging hardware designs using dynamic dependency graphs. Microprocess. Microsystems 47 (2016)
Pascal Pieper, Fabian Greif, Görschwin Fey
Umgebung für automatisierte Tests von Dateisystemen auf NAND-Flash-Speichern. Echtzeit (2016)
Niels Thole, Heinz Riener, Görschwin Fey
Equivalence checking on ESL utilizing a priori knowledge. FDL (2016)
Heinz Riener, Görschwin Fey
Exact diagnosis using boolean satisfiability. ICCAD (2016)
Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL (2016)
Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, Jan-Gerd Mess, Robert Schmidt
On the robustness of DCT-based compression algorithms for space applications. IOLTS (2016)
Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
SMT-Based CPS Parameter Synthesis. ARCH@CPSWeek (2016)
Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. LATS (2016)
Niklas Krafczyk, Heinz Riener, Görschwin Fey
WCET overapproximation for software in the context of a Cyber-Physical System. VLSI-SoC (2016)
Niels Thole, Görschwin Fey
Formal Verification of Robustness. SyDe Summer School (2015)
Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
Execution Tracing of C Code for Formal Analysis (Extended Abstract). MBMV (2015)
Mehdi Dehbashi, Görschwin Fey
Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocess. Microsystems 39 (3) (2015)
Niels Thole, Görschwin Fey, Alberto García Ortiz
Conservatively Analyzing Transient Faults. ISVLSI (2015)
Tino Flenker, André Sülflow, Görschwin Fey
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. ATS (2015)
Niels Thole, Heinz Riener, Görschwin Fey
Equivalence Checking on System Level Using a Priori Knowledge. DDECS (2015)
Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Path-Based Program Repair. FESCA (2015)
Gökçe Aydos, Görschwin Fey
In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR. SyDe Summer School (2015)
Gökçe Aydos, Görschwin Fey
Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture. GI-Jahrestagung (2015)
Gökçe Aydos, Görschwin Fey
Empirical results on parity-based soft error detection with software-based retry. NORCAS (2015)
Mehdi Dehbashi, Görschwin Fey
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. PDP (2014)
Niels Thole, Görschwin Fey
Equivalence Checking on System Level using Stepwise Induction. MBMV (2014)
Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
A Logic for Cardinality Constraints (Extended Abstract). MBMV (2014)
Mehdi Dehbashi, Görschwin Fey
Debug Automation for Synchronization Bugs at RTL. VLSI Design (2014)
Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey
Mutation Based Feature Localization. MTV (2014)
Jan Malburg, Niklas Krafczyk, Görschwin Fey
Automatically connecting hardware blocks via light-weight matching techniques. DDECS (2014)
Alexander Finder, André Sülflow, Görschwin Fey
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Mehdi Dehbashi, Görschwin Fey
SAT-based speedpath debugging using X traces. IDT (2014)
Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
MetaSMT: a unified interface to SMT-LIB2. FDL (2014)
Jan Malburg, Alexander Finder, Görschwin Fey
A Simulation-Based Approach for Automated Feature Localization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Mehdi Dehbashi, Görschwin Fey
Sat-based speedpath debugging using waveforms. ETS (2014)
Heinz Riener, Görschwin Fey
Yet a Better Error Explanation Algorithm (Extended Abstract). MBMV (2013)
Mehdi Dehbashi, André Sülflow, Görschwin Fey
Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems 37 (2) (2013)
Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
Reliability analysis reloaded: how will we survive? DATE (2013)
Mehdi Dehbashi, Görschwin Fey
Debug Automation for Logic Circuits Under Timing Variations. IEEE Des. Test 30 (6) (2013)
Jan Malburg, Alexander Finder, Görschwin Fey
Tuning dynamic data flow analysis to support design understanding. DATE (2013)
Mehdi Dehbashi, Görschwin Fey
Efficient automated speedpath debugging. DDECS (2013)
Daniel Große, Görschwin Fey, Rolf Drechsler
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 62 (2013)
Heinz Riener, Stefan Frehse, Görschwin Fey
Improving fault tolerance utilizing hardware-software-co-synthesis. DATE (2013)
Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Debugging HDL designs based on functional equivalences with high-level specifications. DDECS (2013)
Jan Malburg, Alexander Finder, Görschwin Fey
Automated feature localization for hardware designs using coverage metrics. DAC (2012)
Mehdi Dehbashi, Görschwin Fey
Automated debugging from pre-silicon to post-silicon. DDECS (2012)
Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Functional analysis of circuits under timing variations. ETS (2012)
Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference (2012)
Jan Malburg, Alexander Finder, Görschwin Fey
Automated Feature Localization for Hardware Designs using Coverage Metrics. MBMV (2012)

Görschwin Fey.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Görschwin Fey