Daniel Große

ORCID

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 109

Top Venues

DATE

ASP-DAC

DAC

ACM Great Lakes Symposium on VLSI

Publications

Manfred Schlägl, Moritz Stockinger, Daniel Große
A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level. DATE (2024)
Christoph Hazott, Florian Stögmüller, Daniel Große
Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. ASPDAC (2024)
Lucas Klemmer, Daniel Große
Towards a Highly Interactive Design-Debug-Verification Cycle. ASPDAC (2024)
Christoph Hazott, Daniel Große
Relation Coverage: A New Paradigm for Hardware/Software Testing. ETS (2024)
Daniel Große, Lucas Klemmer, Dominik Bonora
Using Formal Verification Methods for Optimization of Circuits Under External Constraints. DATE (2024)
Manfred Schlägl, Daniel Große
GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. ACM Great Lakes Symposium on VLSI (2023)
Frans Skarman, Lucas Klemmer, Oscar Gustafsson, Daniel Große
Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis. FDL (2023)
Katharina Ruep, Daniel Große
Improving Design Understanding of Processors leveraging Datapath Clustering. DATE (2023)
Lucas Klemmer, Daniel Große
Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV. CoRR (2023)
Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC (2022)
Lucas Klemmer, Daniel Große
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle. ISVLSI (2022)
Lucas Klemmer, Daniel Große
Waveform-based performance analysis of RISC-V processors: late breaking results. DAC (2022)
Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD (2022)
Alireza Mahzoon, Daniel Große, Rolf Drechsler
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC (2022)
Lucas Klemmer, Manfred Schlägl, Daniel Große
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. ACM Great Lakes Symposium on VLSI (2022)
Lucas Klemmer, Sonja Gurtner, Daniel Große
Formal Verification of SUBLEQ Microcode implementing the RV32I ISA. FDL (2022)
Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI (2022)
Katharina Ruep, Daniel Große
SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. ETS (2022)
Lucas Klemmer, Daniel Große
WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging. ASP-DAC (2022)
Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
Mutation-based Compliance Testing for RISC-V. ASP-DAC (2021)
Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC (2021)
Muhammad Hassan, Daniel Große, Rolf Drechsler
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. ASP-DAC (2021)
Muhammad Hassan, Daniel Große, Rolf Drechsler
System Level Verification of Phase-Locked Loop using Metamorphic Relations. DATE (2021)
Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. ISCAS (2021)
Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE (2021)
Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. 13 (4) (2021)
Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116 (2021)
Lucas Klemmer, Daniel Große
EPEX: Processor Verification by Equivalent Program Execution. ACM Great Lakes Symposium on VLSI (2021)
David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS (2020)
Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL (2020)
Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD (2020)
Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) (2020)
Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler
RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. 109 (2020)
Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks. ISMVL (2020)
Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler
Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning. IFM (2020)
Niklas Bruns, Daniel Große, Rolf Drechsler
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. ACM Great Lakes Symposium on VLSI (2020)
Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Verification for Field-coupled Nanocomputing Circuits. DAC (2020)
Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC (2020)
Vladimir Herdt, Daniel Große, Rolf Drechsler
. DATE (2020)
Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Marcel Walter, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. Microprocess. Microsystems 76 (2020)
Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI (2020)
Vladimir Herdt, Daniel Große, Rolf Drechsler
. DATE (2020)
Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Towards Formal Verification of Optimized and Industrial Multipliers. DATE (2020)
Vladimir Herdt, Daniel Große, Rolf Drechsler
RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA (2020)
Vladimir Herdt, Daniel Große, Rolf Drechsler
. DAC (2020)
Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC (2019)
Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Functional Coverage-Driven Characterization of RF Amplifiers. FDL (2019)
Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
Data Flow Testing for SystemC-AMS Timed Data Flow Models. DATE (2019)
Rolf Drechsler, Daniel Große
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. ATS (2019)
Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD (2019)
Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. CoRR (2019)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Maximizing power state cross coverage in firmware-based power management. ASP-DAC (2019)
Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. ARC (2019)
Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
. FDL (2019)
Saman Fröhlich, Daniel Große, Rolf Drechsler
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. DATE (2019)
Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
. DATE (2019)
Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. ISVLSI (2019)
Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. 61 (1) (2019)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. 21 (5) (2019)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (7) (2019)
Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler
SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD (2019)
Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
-complete (Research Note). ACM J. Emerg. Technol. Comput. Syst. 15 (3) (2019)
Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI (2019)
Alireza Mahzoon, Daniel Große, Rolf Drechsler
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC (2019)
Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. DATE (2019)
Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Scalable design for field-coupled nanocomputing circuits. ASP-DAC (2019)
Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018)
David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
. NORCAS (2018)
Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Extensible and Configurable RISC-V Based Virtual Prototype. FDL (2018)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Towards Automated Refinement of TLM Properties to RTL. MBMV (2018)
David Lemma, Daniel Große, Rolf Drechsler
Natural Language Based Power Domain Partitioning. DDECS (2018)
Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Resilience evaluation via symbolic fault injection on intermediate code. DATE (2018)
Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Approximation-aware testing for approximate circuits. ASP-DAC (2018)
Alireza Mahzoon, Daniel Große, Rolf Drechsler
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD (2018)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Towards fully automated TLM-to-RTL property refinement. DATE (2018)
Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. DSD (2018)
Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Testbench qualification for SystemC-AMS timed data flow models. DATE (2018)
Saman Fröhlich, Daniel Große, Rolf Drechsler
Approximate hardware generation using symbolic computer algebra employing grobner basis. DATE (2018)
Saman Fröhlich, Daniel Große, Rolf Drechsler
Towards Reversed Approximate Hardware Design. DSD (2018)
Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI (2018)
Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. ISVLSI (2018)
Alireza Mahzoon, Daniel Große, Rolf Drechsler
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI (2018)
Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
An exact method for design exploration of quantum-dot cellular automata. DATE (2018)
Arun Chandrasekharan, Daniel Große, Rolf Drechsler
ProACt: A Processor for High Performance On-demand Approximate Computing. ACM Great Lakes Symposium on VLSI (2017)
Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19 (5) (2017)
Saman Fröhlich, Daniel Große, Rolf Drechsler
Error Bounded Exact BDD Minimization in Approximate Computing. ISMVL (2017)
Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. FORMATS (2017)
Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. ASP-DAC (2017)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) (2017)
Saman Fröhlich, Daniel Große, Rolf Drechsler
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. MBMV (2017)
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
-preferred evolutionary algorithm for approximate BDD optimization. GECCO (2017)
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Early SoC security validation by VP-based static information flow analysis. ICCAD (2017)
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Data flow testing for virtual prototypes. DATE (2017)
Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL (2017)
Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Yise - a novel framework for boolean networks using y-inverter graphs. MEMOCODE (2017)
Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Quantitative timing analysis of UML activity diagrams using statistical model checking. DATE (2016)
Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Equivalence checking using Gröbner bases. FMCAD (2016)
Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
BDD minimization for approximate computing. ASP-DAC (2016)
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) (2016)

Daniel Große.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Daniel Große