Sebastian Huhn

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 24

Top Topics

Boolean Satisfiability

Quality Assessment

Top Venues

Publications

Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler
A Multi-Objective Evolutionary Approach for Test Network Design. ETS (2024)
Payam Habiby, Sebastian Huhn, Rolf Drechsler
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. DFT (2023)
Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. ETS (2023)
Daniel Tille, Leon Klimasch, Sebastian Huhn
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. VTS (2023)
Marcel Merten, Sebastian Huhn, Rolf Drechsler
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. ETS (2023)
Sebastian Huhn, Rolf Drechsler
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. ITC (2022)
Marcel Merten, Sebastian Huhn, Rolf Drechsler
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. ETS (2022)
Marcel Merten, Sebastian Huhn, Rolf Drechsler
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. VTS (2022)
Marcel Merten, Sebastian Huhn, Rolf Drechsler
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. DFT (2021)
Payam Habiby, Sebastian Huhn, Rolf Drechsler
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. DTIS (2021)
Payam Habiby, Sebastian Huhn, Rolf Drechsler
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains. DFT (2020)
Rolf Drechsler, Sebastian Huhn, Christina Plump
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials. DSD (2020)
Sebastian Huhn, Daniel Tille, Rolf Drechsler
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. ETS (2019)
Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler
SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD (2019)
Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Sebastian Huhn, Daniel Tille, Rolf Drechsler
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. ITC-Asia (2019)
Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI (2018)
Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems. LDIC (2018)
Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE (2017)
Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI (2017)
Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
Reconfigurable TAP controllers with embedded compression for large test data volume. DFT (2017)
Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. ASP-DAC (2017)
Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS (2016)
Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Exploring superior structural materials using multi-objective optimization and formal techniques. ISED (2016)