Daniel Tille

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 13

Top Topics

Routing Overhead

Statistical Tests

Formal Verification

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Daniel Tille, Leon Klimasch, Sebastian Huhn
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. VTS (2023)
Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators. DFT (2023)
Tobias Kilian, Daniel Tille, Martin Huch, Markus Hanel, Ulf Schlichtmann
Performance Screening Using Functional Path Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann
Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators. ETS (2022)
Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data. ITC (2022)
Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators. ITC (2021)
Sebastian Huhn, Daniel Tille, Rolf Drechsler
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. ETS (2019)
Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki
Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC (2019)
Sebastian Huhn, Daniel Tille, Rolf Drechsler
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. ITC-Asia (2019)
Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann
On enabling diagnosis for 1-Pin Test fails in an industrial flow. ASP-DAC (2018)
Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen
A lightweight X-masking scheme for IoT designs. ITC-Asia (2017)
Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS (2016)
Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Automated formal verification of X propagation with respect to testability issues. IDT (2014)
Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS (2010)
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS (2010)
Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Daniel Tille, Rolf Drechsler
A fast untestability proof for SAT-based ATPG. DDECS (2009)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51 (2) (2009)
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium (2009)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation (2008)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Daniel Tille, Rolf Drechsler
Incremental SAT Instance Generation for SAT-based ATPG. DDECS (2008)
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL (2007)
Daniel Tille, Görschwin Fey, Rolf Drechsler
Instance Generation for SAT-based ATPG. DDECS (2007)