Kohei Miyase

Publication Activity (10 Years)

Years Active: 2001-2022
Publications (10 Years): 20

Top Topics

Subgraph Isomorphism

Power Reduction

Test Generation

Top Venues

IEICE Trans. Inf. Syst.

Publications

Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase
Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC-Asia (2022)
Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara
A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications. ITC (2022)
Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase
Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC (2022)
Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia (2022)
Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase
Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories. ITC (2022)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase, Chun-Lung Hsu, Chi-Tien Sun
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. J. Electron. Test. 37 (4) (2021)
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. IEICE Trans. Inf. Syst. (6) (2021)
Aibin Yan, Xiangfeng Feng, Yuanjie Hu, Chaoping Lai, Jie Cui, Zhili Chen, Kohei Miyase, Xiaoqing Wen
Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments. IEEE Trans. Aerosp. Electron. Syst. 56 (2) (2020)
Chihiro Koga, Kohei Miyase, Masato Tokui
Analyzing Running Form with Acceleration Sensor. ICCE (2020)
Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. J. Electron. Test. 35 (4) (2019)
Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia (2019)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory. IOLTS (2018)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase
Progressive ECC Techniques for Phase Change Memory. ATS (2018)
Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. ATS (2018)
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. ATS (2017)
Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
Analysis and mitigation or IR-Drop induced scan shift-errors. ITC (2017)
Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
SAT-based post-processing for regional capture power reduction in at-speed scan test generation. ETS (2016)
Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
On Optimal Power-Aware Path Sensitization. ATS (2016)
Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS (2016)
Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
K. Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, J. Qian
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS (2015)
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase
A soft-error tolerant TCAM using partial don't-care keys. ETS (2015)
Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
Identification of high power consuming areas with gate type and logic level information. ETS (2015)
Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. (10) (2014)
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase
Soft-error tolerant TCAMs for high-reliability packet classifications. APCCAS (2014)
Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design (2013)
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. (9) (2013)
Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
Search Space Reduction for Low-Power Test Generation. Asian Test Symposium (2013)
Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test 30 (4) (2013)
Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. (9) (2013)
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium (2012)
Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS (2012)
Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On pinpoint capture power management in at-speed scan test generation. ITC (2012)
Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium (2012)
Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium (2011)
Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED (2011)
Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC (2011)
Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
Transition-Time-Relation based capture-safety checking for at-speed scan test generation. DATE (2011)
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. (6) (2011)
Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing. IEICE Trans. Inf. Syst. (4) (2011)
Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich
Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium (2011)
Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor
Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS (2011)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium (2011)
Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
Is test power reduction through X-filling good enough? ITC (2010)
Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
On estimation of NBTI-Induced delay degradation. ETS (2010)
Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. (1) (2010)
Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium (2009)
Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD (2009)
Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC (2009)
Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS (2008)
Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara
-Fault Model for Deep-Submicron LSI Circuits. IEICE Trans. Inf. Syst. (3) (2008)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24 (4) (2008)
Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS (2008)
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS (2008)
Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy
On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. (3) (2008)
Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. ITC (2008)
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD (2008)
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC (2007)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC (2007)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. (9) (2007)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD (2006)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
-Fault Model. IEICE Trans. Inf. Syst. (11) (2006)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS (2006)
Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. 1 (3) (2005)
Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy
On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium (2005)
Kohei Miyase, Seiji Kajihara
XID: Don't care identification of test patterns for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Trans. Inf. Syst. (3) (2004)
Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium (2004)
Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8 (4) (2003)
Kohei Miyase, Seiji Kajihara
Optimal Scan Tree Construction with Test Vector Modification for Test Compression. Asian Test Symposium (2003)
Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
Don't-Care Identification on Specific Bits of Test Patterns. ICCD (2002)
Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium (2002)
Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy
A Method of Static Test Compaction Based on Don't Care Identification. DELTA (2002)
Seiji Kajihara, Koji Ishida, Kohei Miyase
Test Vector Modification for Power Reduction during Scan Testing. VTS (2002)
Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS (2002)
Seiji Kajihara, Kohei Miyase
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. ICCAD (2001)