Serge Pravossoudovitch

Publication Activity (10 Years)

Years Active: 1990-2018
Publications (10 Years): 2

Top Venues

J. Electron. Test.

ISVLSI

IWASI

NEWCAS

Publications

Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS (2018)
Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32 (2) (2016)
Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI (2015)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30 (4) (2014)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
Intra-Cell Defects Diagnosis. J. Electron. Test. 30 (5) (2014)
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS (2014)
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI (2014)
Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS (2013)
Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS (2013)
Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS (2013)
Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI (2013)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced test methods for SRAMs. VTS (2012)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28 (3) (2012)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
eFlash Memories. J. Electron. Test. 28 (2) (2012)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium (2011)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS (2011)
Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT (2011)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
On using address scrambling to implement defect tolerance in SRAMs. ITC (2011)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS (2011)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium (2011)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS (2011)
Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT (2011)
Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS (2011)
Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
An Exact and Efficient Critical Path Tracing Algorithm. DELTA (2010)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
eFlash memory technology for defect injection and faulty behavior prediction. ETS (2010)
Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
Is test power reduction through X-filling good enough? ITC (2010)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
A statistical simulation method for reliability analysis of SRAM core-cells. DAC (2010)
Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium (2010)
Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59 (3) (2010)
Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium (2010)
Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6 (2) (2010)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
Parity prediction synthesis for nano-electronic gate designs. ITC (2010)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Setting test conditions for improving SRAM reliability. ETS (2010)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Detecting NBTI induced failures in SRAM core-cells. VTS (2010)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS (2010)
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA (2010)
Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS (2010)
Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS (2009)
Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 17 (10) (2009)
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. 25 (2-3) (2009)
Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
A case study on logic diagnosis for System-on-Chip. ISQED (2009)
Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
A new design-for-test technique for SRAM core-cell stability faults. DATE (2009)
Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium (2009)
Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3 (6) (2009)
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard
NAND flash testing: A preliminary study on actual defects. ITC (2009)
Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS (2009)
Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE (2008)
Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC (2008)
Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi
SoC Symbolic Simulation: a case study on delay fault testing. DDECS (2008)
Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS (2008)
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Using TMR Architectures for Yield Improvement. DFT (2008)
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
SoC Yield Improvement: Redundant Architectures to the Rescue? ITC (2008)
Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. 24 (4) (2008)
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS (2008)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Improving Diagnosis Resolution without Physical Information. DELTA (2008)
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE (2007)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. 23 (5) (2007)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Fast Bridging Fault Diagnosis using Logic Information. ATS (2007)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
DERRIC: A Tool for Unified Logic Diagnosis. ETS (2007)
Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga
A concurrent approach for testing address decoder faults in eFlash memories. ITC (2007)
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS (2007)
Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS (2007)
Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Mixed Approach for Unified Logic Diagnosis. DDECS (2007)
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS (2007)
Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS (2007)
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS (2007)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22 (1) (2006)
Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault
Power-Aware Test Data Compression for Embedded IP Cores. ATS (2006)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. 22 (2) (2006)
Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
An Overview of Failure Mechanisms in Embedded Flash Memories. VTS (2006)
Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC (2006)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. 22 (3) (2006)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS (2006)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC (2005)
Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC (2005)
Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS (2005)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. 21 (1) (2005)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS (2005)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. 21 (5) (2005)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS (2005)
Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. 21 (2) (2005)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. 20 (6) (2004)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DATE (2004)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Design of Routing-Constrained Low Power Scan Chains. DELTA (2004)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS (2004)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
March iC-: An Improved Version of March C- for ADOFs Detection. VTS (2004)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS (2004)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium (2004)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW (2003)
Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium (2003)
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS (2003)
Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Defect-oriented dynamic fault models for embedded-SRAMs. ETW (2003)
Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC (2003)
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Power Driven Chaining of Flip-Flops in Scan Architectures. ITC (2002)
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. 19 (5) (2002)
René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
On Using Efficient Test Sequences for BIST. VTS (2002)
René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. 18 (2) (2002)
Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Test Power: a Big Issue in Large SOC Designs. DELTA (2002)

Serge Pravossoudovitch.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Serge Pravossoudovitch