High Defect Coverage with Low-Power Test Sequences in a BIST Environment.
Patrick GirardChristian LandraultSerge PravossoudovitchArnaud VirazelHans-Joachim WunderlichPublished in: IEEE Des. Test Comput. (2002)
Keyphrases
- low power
- test sequences
- low cost
- power consumption
- high speed
- low power consumption
- high power
- real time
- test cases
- bit rate
- test suite
- video sequences
- vlsi circuits
- single chip
- logic circuits
- vlsi architecture
- digital signal processing
- wireless transmission
- gate array
- cmos technology
- image sensor
- power reduction
- mixed signal
- database systems