Arnaud Virazel

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 57

Top Venues

Publications

Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE (2024)
G. Mongelli, Xhesila Xhafa, Eric Faehn, D. Robins, P. Girard, Arnaud Virazel
A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. IOLTS (2024)
Xhesila Xhafa, Patrick Girard, Arnaud Virazel
Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. ETS (2023)
J. Lefevre, P. Debaud, P. Girard, Arnaud Virazel
Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. ITC (2023)
L. Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS (2023)
Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS (2023)
S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS (2022)
P. D'Hondt, A. Ladhar, P. Girard, Arnaud Virazel
A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. ITC (2022)
Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS (2022)
J. Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel
A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. ETS (2022)
S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED (2021)
J. Lefevre, Philippe Debaud, Patrick Girard, Arnaud Virazel
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. ITC (2021)
S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS (2021)
Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS (2021)
Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS (2021)
Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
P. d'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. DATE (2021)
Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
. ETS (2021)
Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109 (2) (2021)
L. Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS (2021)
S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC (2020)
Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS (2020)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Maximizing Yield for Approximate Integrated Circuits. DATE (2020)
Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS (2020)
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36 (1) (2020)
Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. IOLTS (2020)
S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS (2020)
Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS (2020)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE 108 (12) (2020)
Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS (2019)
Hassen Aziza, Mathieu Moreau, Annie Pérez, Arnaud Virazel, Patrick Girard
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. NEWCAS (2019)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Testing approximate digital circuits: Challenges and opportunities. LATS (2018)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT (2018)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6 (2) (2018)
Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS (2018)
Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC (2018)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS (2018)
Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Towards approximation during test of Integrated Circuits. DDECS (2017)
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Towards digital circuit approximation by exploiting fault simulation. EWDTS (2017)
G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
An effective fault-injection framework for memory reliability enhancement perspectives. DTIS (2017)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26 (8) (2017)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13 (1) (2017)
Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi
Approximate computing: Design & test for integrated circuits. LATS (2017)
Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33 (1) (2017)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26 (8) (2017)
Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel
Auto-adaptive ultra-low power IC. DTIS (2016)
Alberto Bosio, Patrick Girard, Arnaud Virazel
Test of low power circuits: Issues and industrial practices. ICECS (2016)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED (2016)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI (2016)
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
An effective approach for functional test programs compaction. DDECS (2016)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC (2016)
Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS (2016)
Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard
An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. J. Electron. Test. 32 (6) (2016)
Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio
Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED (2016)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
A hybrid power modeling approach to enhance high-level power models. DDECS (2016)
Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32 (2) (2016)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25 (3) (2016)
Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
An effective hybrid fault-tolerant architecture for pipelined cores. ETS (2015)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
An effective ATPG flow for Gate Delay Faults. DTIS (2015)
Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED (2015)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot
Design-for-Diagnosis Architecture for Power Switches. DDECS (2015)
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Scan-chain intra-cell defects grading. DTIS (2015)
Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS (2015)
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
Exploring the impact of functional test programs re-used for power-aware testing. DATE (2015)
Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI (2015)
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM (2015)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
Test and diagnosis of power switches. DDECS (2014)
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30 (4) (2014)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
Intra-Cell Defects Diagnosis. J. Electron. Test. 30 (5) (2014)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS (2014)
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS (2014)
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
iBoX - Jitter based Power Supply Noise sensor. ETS (2014)
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW (2014)
Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI (2014)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Timing-aware ATPG for critical paths with multiple TSVs. DDECS (2014)
Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS (2014)
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC (2014)
Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS (2014)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
An intra-cell defect grading tool. DDECS (2014)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30 (5) (2014)
Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium (2013)
Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS (2013)
Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS (2013)
Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS (2013)
Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI (2013)
Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC (2013)
Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS (2013)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Test solution for data retention faults in low-power SRAMs. DATE (2013)
Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI (2013)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
Computing detection probability of delay defects in signal line tsvs. ETS (2013)
Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS (2013)
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray
Effect-cause intra-cell diagnosis at transistor level. ISQED (2013)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS (2013)
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel
Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium (2012)
Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS (2012)
Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
Defect analysis in power mode control logic of low-power SRAMs. ETS (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Arnaud Virazel