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Cyril Chevalier
Publication Activity (10 Years)
Years Active: 1993-2017
Publications (10 Years): 4
Top Topics
Hybrid Models
Power System
Monte Carlo Simulation
Statistical Models
Top Venues
VLSI-SoC
ICECS
DDECS
J. Low Power Electron.
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Publications
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Alejandro Nocua
,
Arnaud Virazel
,
Alberto Bosio
,
Patrick Girard
,
Cyril Chevalier
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality.
J. Low Power Electron.
13 (1) (2017)
Alejandro Nocua
,
Arnaud Virazel
,
Alberto Bosio
,
Patrick Girard
,
Cyril Chevalier
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization.
J. Circuits Syst. Comput.
26 (8) (2017)
Alejandro Nocua
,
Arnaud Virazel
,
Alberto Bosio
,
Patrick Girard
,
Cyril Chevalier
A Hybrid Power Estimation Technique to improve IP power models quality.
VLSI-SoC
(2016)
Alejandro Nocua
,
Arnaud Virazel
,
Alberto Bosio
,
Patrick Girard
,
Cyril Chevalier
A hybrid power modeling approach to enhance high-level power models.
DDECS
(2016)
Chadi Al Khatib
,
Claire Aupetit
,
Cyril Chevalier
,
Chouki Aktouf
,
Gilles Sicard
,
Laurent Fesquet
A generic clock controller for low power systems: Experimentation on an AXI bus.
VLSI-SoC
(2015)
Alejandro Nocua
,
Arnaud Virazel
,
Alberto Bosio
,
Patrick Girard
,
Cyril Chevalier
An efficient hybrid power modeling approach for accurate gate-level power estimation.
ICM
(2015)
Chadi Al Khatib
,
Claire Aupetit
,
Alejandro Chagoya
,
Cyril Chevalier
,
Gilles Sicard
,
Laurent Fesquet
Distributed asynchronous controllers for clock management in low power systems.
ICECS
(2014)
Christian Dufaza
,
H. Viallon
,
Cyril Chevalier
BIST hardware generator for mixed test scheme.
ED&TC
(1995)
Christian Dufaza
,
Cyril Chevalier
,
Lew Fock Chong Lew Yan Voon
LFSROM an algorithm for automatic design synthesis of hardware test pattern generator.
VTS
(1993)