Laurent Fesquet

ORCID

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 67

Top Venues

Publications

Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet
Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC (2023)
Xavier Lesage, Rosalie Tran, Stéphane Mancini, Laurent Fesquet
Velocity and Color Estimation Using Event-Based Clustering. Sensors 23 (24) (2023)
Laurent Fesquet, Rosalie Tran, Xavier Lesage, Mohamed Akrarai, Stéphane Mancini, Gilles Sicard
Low-Throughput Event-Based Image Sensors and Processing. DATE (2023)
Diana Kalel, Jean-Christophe Brignone, Laurent Fesquet, Katell Morin-Allory
A Generic CDC Modeling for Data Stability Verification. ICECS (2023)
Hasan Moussa, Jessica Gonsalves, Estelle Lauga-Larroze, Sana Ibrahim, Florence Podevin, Sylvain Bourdel, Laurent Fesquet
Making Digital N-Path Mixers. DCIS (2023)
Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
A Novel Event-Based Method for ASK Demodulation. LASCAS (2022)
Xavier Lesage, Rosalie Tran, Stéphane Mancini, Laurent Fesquet
An improved event-by-event clustering algorithm for noisy acquisition. EBCCSP (2022)
Ali Al Shakoush, Sana Ibrahim, Serge Subias, Florence Podevin, Manuel J. Barragan, Dayana A. Pino-Monroy, Imadeddine Bendjeddou, Estelle Lauga-Larroze, Laurent Fesquet, Thierry Taris, Sylvain Bourdel
Harmonic for Low Power Multi-standard Receivers. NEWCAS (2022)
Hasan Moussa, Sana Ibrahim, Estelle Lauga-Larroze, Florence Podevin, Sylvain Bourdel, Laurent Fesquet
Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis. NEWCAS (2022)
Enagnon Aguénounon, Safa Razavinejad, Jean-Baptiste Schell, Mohammadreza Dolatpoor Lakeh, Wassim Khaddour, Foudil Dadouche, Jean-Baptiste Kammerer, Laurent Fesquet, Wilfried Uhring
Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout. Sensors 21 (12) (2021)
Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. ICECS (2021)
Assia El-Hadbi, Oussama Elissati, Laurent Fesquet
Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35μ m CMOS Proof-of-Concept Prototype. I2MTC (2021)
Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. EBCCSP (2021)
Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. IEEE Des. Test 38 (6) (2021)
Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. VLSI-SoC (2021)
Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
A hybrid event-based pixel for low-power image sensing. ICECS (2021)
Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
An asynchronous hybrid pixel image sensor. ASYNC (2021)
Ricardo Aquino Guazzelli, Matheus Garay Trindade, Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos
Trojan Detection Test for Clockless Circuits. J. Electron. Test. 36 (1) (2020)
Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet
A Self-Timed Ring based PUF. ASYNC (2020)
Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression. EBCCSP (2020)
Ricardo Aquino Guazzelli, Laurent Fesquet
At-speed DfT Architecture for Bundled-data Design. ITC (2020)
Saeed Mian Qaisar, Laurent Fesquet
An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection. EBCCSP (2020)
Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet
From High-Level Synthesis to Bundled-Data Circuits. SAMOS (2020)
Mohamed Akrarai, Nils Margotat, Gilles Sicard, Laurent Fesquet
A Novel Event Based Image Sensor with spacial and temporal redundancy suppression. NEWCAS (2020)
Ali Al Shakoush, Estelle Lauga-Larroze, Florence Podevin, Sana Ibrahim, Laurent Fesquet, Sylvain Bourdel
Improved $\pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver. NEWCAS (2020)
Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels
A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC (2019)
Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
A Digital Event-Based Strategy for ASK demodulation. VLSI-SoC (2019)
Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
An Event-Based Strategy for ASK demodulation. EBCCSP (2019)
Olivier Bonnaud, Laurent Fesquet, Ahmad Bsiesy
Skilled manpower shortage in microelectronics: a challenge for the French education microelectronics network. ITHET (2019)
Brigitte Bidégaray-Fesquet, Laurent Fesquet
A new synthesis approach for non-uniform filters in the log-scale: Proof of concept. EBCCSP (2019)
Grégoire Gimenez, Jean Simatic, Laurent Fesquet
From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. ASYNC (2019)
Ali Skaf, Mona Ezzadeen, Mounir Benabdenbi, Laurent Fesquet
On-Line Adjustable Precision Computing. DTIS (2019)
Assia El-Hadbi, Oussama Elissati, Laurent Fesquet
Time-to-Digital Converters: A Literature Review and New Perspectives. EBCCSP (2019)
Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet
Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP (2019)
Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC (2018)
Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. DCIS (2018)
Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos
A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems. Microelectron. Reliab. (2018)
Raphael Frisch, Marvin Faix, Emmanuel Mazer, Laurent Fesquet, Augustin Lux
A Cognitive Stochastic Machine Based on Bayesian Inference: A Behavioral Analysis. ICCI*CC (2018)
Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal
Subthreshold logic for low-area and energy efficient true random number generator. COOL CHIPS (2018)
Rodrigo Possamai Bastos, Leonel Acunha Guimaraes, Frank Sill Torres, Laurent Fesquet
Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits. Microelectron. J. 71 (2018)
Timothe Turko, Wilfried Uhring, Foudil Dadouche, Laurent Fesquet
An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems. ICECS (2018)
Olivier Bonnaud, Laurent Fesquet, Luc Hébrard
Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society. LASCAS (2018)
Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet
Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. ISCAS (2018)
Sophie Germain, Sylvain Engels, Laurent Fesquet
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ASYNC (2018)
Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Laurent Fesquet
Non-intrusive testing technique for detection of Trojans in asynchronous circuits. DATE (2018)
Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC (2017)
Arthur Kalsing, Laurent Fesquet, Chouki Aktouf
Towards consistency checking between HDL and UPF descriptions. FDL (2017)
Amani Darwish, Hassan Abbass, Laurent Fesquet, Gilles Sicard
Event-driven image sensor application: Event-driven image segmentation. EBCCSP (2017)
Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet
Self-timed Ring based True Random Number Generator: Threat model and countermeasures. IVSW (2017)
Sophie Germain, Sylvain Engels, Laurent Fesquet
Event-based design strategy for circuit electromagnetic compatibility. EBCCSP (2017)
Arthur Kalsing, Laurent Fesquet, Chouki Aktouf
A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. FDL (Selected Papers) (2017)
Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS (2017)
Saeed Mian Qaisar, Jean Simatic, Laurent Fesquet
High-level synthesis of an event-driven windowing process. EBCCSP (2017)
Raphael Frisch, Raphaël Laurent, Marvin Faix, Laurent Girin, Laurent Fesquet, Augustin Lux, Jacques Droulez, Pierre Bessière, Emmanuel Mazer
A Bayesian Stochastic Machine for Sound Source Localization. ICRC (2017)
Olivier Bonnaud, Laurent Fesquet
Innovative practice in the French microelectronics education targeting the industrial needs. MSE (2017)
Ali Skaf, Jean Simatic, Laurent Fesquet
Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. ISCAS (2017)
François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet
CAR: On the highway towards de-synchronization. ICECS (2017)
Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Laurent Fesquet
Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. ISVLSI (2017)
A. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet
Delay partitioning helps reducing variability in 3DVLSI. ESSCIRC (2016)
Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Laurent Fesquet
Simple tri-state logic Trojans able to upset properties of ring oscillators. DTIS (2016)
Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI (2016)
Jean Simatic, Rodrigo Possamai Bastos, Laurent Fesquet
High-level synthesis for event-based systems. EBCCSP (2016)
Olivier Bonnaud, Laurent Fesquet
MOOC and practices in electrical and information engineering: Complementary approaches. ITHET (2016)
Olivier Bonnaud, Laurent Fesquet
Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network. EWME (2016)
Taha Beyrouthy, Ahmed Roshdy, Mohammad Salman, Saeed Mian Qaisar, Laurent Fesquet
Asynchronous implementation of an event-driven adaptive FIR filter. EBCCSP (2016)
Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Rodrigo Iga Jadue, Laurent Fesquet
Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits. PATMOS (2016)
Brigitte Bidégaray-Fesquet, Laurent Fesquet
Levels, peaks, slopes... which sampling for which purpose? EBCCSP (2016)
Olivier Bonnaud, Laurent Fesquet
Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications. ITHET (2015)
Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet
A generic clock controller for low power systems: Experimentation on an AXI bus. VLSI-SoC (2015)
Cansu Arslan, Julien Poujaud, Laurent Fesquet
A method to automatically determine the level-crossing thresholds in non-uniform sampling and processing. EBCCSP (2015)
Otto Aureliano Rolloff, Rodrigo Possamai Bastos, Laurent Fesquet
Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. Microelectron. Reliab. 55 (9-10) (2015)
Taha Beyrouthy, Laurent Fesquet, Robin Rolland
Data sampling and processing: Uniform vs. non-uniform schemes. EBCCSP (2015)
Amani Darwish, Laurent Fesquet, Gilles Sicard
RTL simulation of an asynchronous reading architecture for an event-driven image sensor. EBCCSP (2015)
Olivier Bonnaud, Laurent Fesquet
Towards multidisciplinarity for microelectronics education: A strategy of the French national network. MSE (2015)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
Adaptive rate filtering a computationally efficient signal processing approach. Signal Process. 94 (2014)
Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati
Self-timed rings as low-phase noise programmable oscillators. NEWCAS (2014)
Olivier Bonnaud, Pascal Nouet, Laurent Fesquet, Taieb Mohammed-Brahim
FINMINA: A French national project to promote innovation in higher education in microelectronics and nanotechnologies. ITHET (2014)
Amani Darwish, Gilles Sicard, Laurent Fesquet
Low data rate architecture for smart image sensor. IMSE (2014)
Olivier Bonnaud, Laurent Fesquet
Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications. EWME (2014)
Chadi Al Khatib, Claire Aupetit, Alejandro Chagoya, Cyril Chevalier, Gilles Sicard, Laurent Fesquet
Distributed asynchronous controllers for clock management in low power systems. ICECS (2014)
Amani Darwish, Laurent Fesquet, Gilles Sicard
1-Level crossing sampling scheme for low data rate image sensors. NEWCAS (2014)
Giuseppe Roa, Tugdual Le Pelleter, Agnès Bonvilain, Alejandro Chagoya, Laurent Fesquet
Designing ultra-low power systems with non-uniform sampling and event-driven logic. SBCCI (2014)
Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC (2013)
Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert
A Very High Speed True Random Number Generator with Entropy Assessment. CHES (2013)
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
A Self-Timed Ring Based True Random Number Generator. ASYNC (2013)
Przemyslaw Sliwinski, Krzysztof S. Berezowski, Pawel Wachel, Gilles Sicard, Laurent Fesquet
Empirical Recovery of Input Nonlinearity in Distributed Element Models. ALCOSP (2013)
Olivier Bonnaud, Laurent Fesquet
Innovating projects as a pedagogical strategy for the French network for education in microélectronics and nanotechnologies. MSE (2013)
Taha Beyrouthy, Laurent Fesquet
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications. Int. J. Reconfigurable Comput. 2013 (2013)
Evelyne Excoffon, Francine Papillon, Laurent Fesquet, Ahmad Bsiesy, Olivier Bonnaud
New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school. ITHET (2012)
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE (2012)
Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya
Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL (2011)
Hatem Zakaria, Laurent Fesquet
Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (2011)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR (2011)
Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory
Formal Verification of C-element Circuits. ASYNC (2011)
Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
C-elements for Hardened Self-timed Circuits. PATMOS (2011)
Taha Beyrouthy, Laurent Fesquet
An event-driven FIR filter: Design and implementation. International Symposium on Rapid System Prototyping (2011)
Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. PATMOS (2010)
Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC (2010)
Laurent Fesquet, Gilles Sicard, Brigitte Bidégaray-Fesquet
Targeting ultra-low power consumption with non-uniform sampling and filtering. ISCAS (2010)
Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. VLSI-SoC (Selected Papers) (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Laurent Fesquet