Abdelkarim Cherkaoui

Publication Activity (10 Years)

Years Active: 2012-2021
Publications (10 Years): 15

Top Topics

Energy Efficient

Top Venues

Publications

Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. ICECS (2021)
Jérémy Belot, Abdelkarim Cherkaoui, Raphaël Laurent, Laurent Fesquet
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. IEEE Des. Test 38 (6) (2021)
Grégoire Gimenez, Abdelkarim Cherkaoui, Laurent Fesquet
A Self-Timed Ring based PUF. ASYNC (2020)
Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ASYNC (2018)
Cédric Marchand, Lilian Bossuet, Ugo Mureddu, Nathalie Bochard, Abdelkarim Cherkaoui, Viktor Fischer
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1) (2018)
Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. DCIS (2018)
Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal
Subthreshold logic for low-area and energy efficient true random number generator. COOL CHIPS (2018)
Jean Simatic, Abdelkarim Cherkaoui, François Bertrand, Rodrigo Possamai Bastos, Laurent Fesquet
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. ASYNC (2017)
Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet
Self-timed Ring based True Random Number Generator: Threat model and countermeasures. IVSW (2017)
Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. NEWCAS (2017)
François Bertrand, Abdelkarim Cherkaoui, Jean Simatic, Anthony Maure, Laurent Fesquet
CAR: On the highway towards de-synchronization. ICECS (2017)
Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. SBCCI (2016)
Abdelkarim Cherkaoui, Lilian Bossuet, Cédric Marchand
Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators. IEEE Trans. Inf. Forensics Secur. 11 (6) (2016)
Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui
Design and Characterization of the TERO-PUF on SRAM FPGAs. ISVLSI (2016)
Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui
Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). FPGA (2016)
Laurent Fesquet, Abdelkarim Cherkaoui, Oussama Elissati
Self-timed rings as low-phase noise programmable oscillators. NEWCAS (2014)
Abdelkarim Cherkaoui, Lilian Bossuet, Ludwig Seitz, Göran Selander, Ravishankar Borgaonkar
New paradigms for access control in constrained environments. ReCoSoC (2014)
Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, Alain Aubert
A Very High Speed True Random Number Generator with Entropy Assessment. CHES (2013)
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
A Self-Timed Ring Based True Random Number Generator. ASYNC (2013)
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. DATE (2012)