Marc Renaudin

Publication Activity (10 Years)

Years Active: 1989-2020
Publications (10 Years): 3

Top Venues

ASYNC

MARS@ETAPS

J. Low Power Electron.

Signal Process.

Publications

Radu Mateescu, Wendelin Serwe, Aymane Bouzafour, Marc Renaudin
Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks. MARS@ETAPS (2020)
Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ASYNC (2018)
Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. J. Low Power Electron. 14 (3) (2018)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
Adaptive rate filtering a computationally efficient signal processing approach. Signal Process. 94 (2014)
Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels
Clockless Design Performance Monitoring for Nanometer Technologies. ASYNC (2014)
Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC (2013)
Alex Yakovlev, Pascal Vivet, Marc Renaudin
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. DATE (2013)
Marc Renaudin, Alain Fonkoua
Tiempo Asynchronous Circuits System Verilog Modeling Language. ASYNC (2012)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR (2011)
Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24 (2) (2011)
Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Trans. Design Autom. Electr. Syst. 16 (3) (2011)
Marc Renaudin
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. PATMOS (2010)
Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP (2010)
Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS (2010)
Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
Evaluating transient-fault effects on traditional C-element's implementations. IOLTS (2010)
Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Microelectron. Reliab. 50 (9-11) (2010)
Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin
Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 17 (7) (2009)
Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin
Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC (2009)
Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS (2009)
Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
Comparing transient-fault effects on synchronous and on asynchronous circuits. IOLTS (2009)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. EURASIP J. Adv. Signal Process. 2009 (2009)
Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED (2009)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC (2008)
Eslam Yahya, Marc Renaudin
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. ICECS (2008)
Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. ASYNC (2008)
Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS (2008)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. J. Electr. Comput. Eng. 2008 (2008)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
Computationally efficient adaptive rate sampling and filtering. EUSIPCO (2007)
Julien Goulier, Eric André, Marc Renaudin
A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC (Selected Papers) (2007)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS (2007)
Sylvain Miermont, Pascal Vivet, Marc Renaudin
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS (2007)
J. Fragoso, Gilles Sicard, Marc Renaudin
Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Tech. Sci. Informatiques 26 (5) (2007)
Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon
Parallel Asynchronous Watershed Algorithm-Architecture. IEEE Trans. Parallel Distributed Syst. 18 (1) (2007)
Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois
The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. SECON (2007)
Eslam Yahya, Marc Renaudin
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. ICECS (2007)
Cedric Koch-Hofer, Marc Renaudin
Timed Asynchronous Circuits Modeling using SystemC. FDL (2007)
Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS (2007)
Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT (2007)
Estelle Labonne, Gilles Sicard, Marc Renaudin
An on-pixel FPN reduction method for a high dynamic range CMO S imager. ESSCIRC (2007)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. ICASSP (3) (2007)
N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
FPGA Architecture for Multi-Style Asynchronous Logic CoRR (2007)
Julien Goulier, Eric André, Marc Renaudin
A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC (2007)
G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
DPA on quasi delay insensitive asynchronous circuits: formalization and improvement CoRR (2007)
Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel
Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC (2006)
Estelle Labonne, Gilles Sicard, Marc Renaudin, Pierre-Damien Berger
A 100dB dynamic range CMOS image sensor with global shutter. ICECS (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55 (9) (2006)
Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
Security evaluation of dual rail logic against DPA attacks. VLSI-SoC (2006)
Eslam Yahya, Marc Renaudin
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS (2006)
Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
Spectral analysis of a signal driven sampling scheme. EUSIPCO (2006)
Marc Renaudin, Yannick Monnet
Asynchronous Design: Fault Robustness and Security Characteristics. IOLTS (2006)
Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin
State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC (2006)
David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin
On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. J. Low Power Electron. 2 (1) (2006)
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES (2006)
D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC (2006)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS (2005)
Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS (2005)
G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC (2005)
David Rios-Arambula, Aurélien Buhrig, Marc Renaudin
Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. PATMOS (2005)
Yasser Ammar, Aurélien Buhrig, Marcin Marzencki, Benoît Charlot, Skandar Basrour, Karine Matou, Marc Renaudin
Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator. sOc-EUSAI (2005)
N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
FPGA Architecture for Multi-Style Asynchronous Logic. DATE (2005)
Laurent Fesquet, Jerome Quartana, Marc Renaudin
Asynchronous Systems on Programmable Logic. ReCoSoC (2005)
Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC (2005)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Asynchronous circuits transient faults sensitivity evaluation. DAC (2005)
G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE (2005)
Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC (2005)
Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric André, Marc Renaudin
A 120nm low power asynchronous ADC. ISLPED (2005)
Jerome Quartana, Laurent Fesquet, Marc Renaudin
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC (2005)
Aurélien Buhrig, Marc Renaudin, Dominique Barthel
Asynchrnous Architecture for Sensor Network Nodes. Med-Hoc-Net (2005)
Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL (2005)
G. Fraidy Bouesse, Marc Renaudin, Adrien Witon, Fabien Germain
A clock-less low-voltage AES crypto-processor. ESSCIRC (2005)
Laurent Fesquet, Marc Renaudin
A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL (2005)
F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin
Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC (2004)
Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain
High Security Smartcards. DATE (2004)
Dhanistha Panyasak, Gilles Sicard, Marc Renaudin
A current shaping methodology for lowering em disturbances in asynchronous circuits. Microelectron. J. 35 (6) (2004)
Yannick Monnet, Marc Renaudin, Régis Leveugle
Asynchronous Circuits Sensitivity to Fault Injection. IOLTS (2004)
Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin
TAST Profiler and Low Energy Asynchronous Design Methodology. PATMOS (2004)
Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin
La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Ann. des Télécommunications 59 (7-8) (2004)
Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC (2003)
Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
Statistic Implementation of QDI Asynchronous Primitives. PATMOS (2003)
Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS (2003)
Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
Validation of Asynchronous Circuit Specifications Using IF/CADP. VLSI-SoC (Selected Papers) (2003)
Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin
A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC (2003)
João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
Automatic Generation of 1-of-M QDI Asynchronous Adders. SBCCI (2003)
João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. PATMOS (2003)
Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS (2002)
Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE (2002)
Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
Implementing Asynchronous Circuits on LUT Based FPGAs. FPL (2002)
Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard
Low-Power Asynchronous A/D Conversion. PATMOS (2002)
Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon
Watershed parallel algorithm for asynchronous processors array. ICME (1) (2002)
Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin
Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS (2002)
Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC (2001)
Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés
Low-power systems on chips (SOCs). DATE (2001)
André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, Pascal Vivet
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. IEEE J. Solid State Circuits 36 (7) (2001)
Marc Renaudin, Pascal Vivet, Frédéric Robin
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC (1999)
Marc Renaudin, Pascal Vivet, Frédéric Robin
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC (1998)
Frédéric Robin, Gilles Privat, Marc Renaudin
Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. Int. J. Pattern Recognit. Artif. Intell. 11 (7) (1997)
Marc Renaudin, Bachar El-Hassan, Alain Guyot
A new asynchronous pipeline scheme: application to the design of a self-timed ring divider. IEEE J. Solid State Circuits 31 (7) (1996)
Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering
Self timed division and square-root extraction. VLSI Design (1996)
Hicham Boutamine, Alain Guyot, Bachar El-Hassan, Marc Renaudin
Asynchronous SRT Dividers: The Real Cost. ED&TC (1996)

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Publication Activity (10 Years)

Top Topics

Top Venues

Marc Renaudin