Tiempo Asynchronous Circuits System Verilog Modeling Language.
Marc RenaudinAlain FonkouaPublished in: ASYNC (2012)
Keyphrases
- modeling language
- asynchronous circuits
- metamodel
- process algebra
- delay insensitive
- formal semantics
- model checking
- design rationale
- hardware designs
- hardware description language
- business process modeling
- artificial intelligence
- black box
- integrated circuit
- formal methods
- educational modeling languages
- uml profile
- reinforcement learning