Paolo Maistri

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 34

Top Topics

Digital Circuits

Homomorphic Encryption

Top Venues

Publications

Nasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification. DATE (2024)
Roua Boulifa, Giorgio Di Natale, Paolo Maistri
Internal State Monitoring in RISC-V Microarchitectures for Security Purpose. LATS (2024)
Sami El Amraoui, Régis Leveugle, Paolo Maistri
Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. DDECS (2024)
Nasr-Eddine Ouldei Tebina, Aghiles Douadi, Luc Salvo, Vincent Beroulle, Nacer-Eddine Zergainoh, Guillaume Hubert, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Maistri
Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation. HOST (2024)
Ihab Alshaer, Gijs Burghoorn, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri
Cross-layer analysis of clock glitch fault injection while fetching variable-length instructions. J. Cryptogr. Eng. 14 (2) (2024)
Aghiles Douadi, Elena Ioana Vatajelu, Paolo Maistri, David Hély, Vincent Beroulle, Giorgio Di Natale
Modeling Thermal Effects For Biasing PUFs. ETS (2024)
Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri
Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection. LATS (2024)
Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri
Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection. CARDIS (2023)
Aghiles Douadi, Giorgio Di Natale, Paolo Maistri, Elena Ioana Vatajelu, Vincent Beroulle
A Study of High Temperature Effects on Ring Oscillator Based Physical Unclonable Functions. IOLTS (2023)
Maryam Esmaeilian, Aghiles Douadi, Zahra Kazemi, Vincent Beroulle, Amir-Pasha Mirbaha, Mahdi Fazeli, Elena Ioana Vatajelu, Paolo Maistri, Giorgio Di Natale
Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack. IOLTS (2023)
Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. DFT (2023)
Nasr-Eddine Ouldei Tebina, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
Ray-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection. IOLTS (2023)
Paolo Maistri, Jiayun Po
A Low-Cost Methodology for EM Fault Emulation on FPGA. DATE (2022)
Michele Portolan, Emanuele Valea, Paolo Maistri, Giorgio Di Natale
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions. IEEE Des. Test 39 (3) (2022)
Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Paolo Maistri
X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective. DFT (2022)
Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri
Variable-Length Instruction Set: Feature or Bug? DSD (2022)
Nicolas Bordes, Paolo Maistri
Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box. DSD (2022)
Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri
Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology. DTIS (2021)
Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle
Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS (2021)
Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale
Security EDA Extension through P1687.1 and 1687 Callbacks. ITC (2021)
Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS (2020)
G. Surya, Paolo Maistri, Sriram Sankaran
Local Clock Glitching Fault Injection with Application to the ASCON Cipher. iSES (2020)
Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle
Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS (2020)
Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW (2019)
Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC (2018)
Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS (2018)
Régis Leveugle, Asma Mkhinini, Paolo Maistri
Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption. Inf. 9 (5) (2018)
Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki
HLS design of a hardware accelerator for Homomorphic Encryption. DDECS (2017)
Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. Microprocess. Microsystems 47 (2016)
Simon Pontie, Paolo Maistri, Régis Leveugle
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance. Microprocess. Microsystems 47 (2016)
Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD (2016)
Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
On the development of a new countermeasure based on a laser attack RTL fault model. DATE (2016)
Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki, Mohsen Machhout
A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption. IDT (2016)
Régis Leveugle, A. Chahed, Paolo Maistri, Athanasios Papadimitriou, David Hély, Vincent Beroulle
On fault injections for early security evaluation vs. laser-based attacks. IVSW (2016)
Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
Validation of RTL laser fault injection model with respect to layout information. HOST (2015)
C. Jayet-Griffon, M.-A. Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle
Polynomial multipliers for fully homomorphic encryption on FPGA. ReConFig (2015)
Matteo Bollo, Paolo Maistri
Composite fields against side channel analysis for the advanced encryption standard. ICECS (2014)
Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart
Electromagnetic analysis and fault injection onto secure circuits. VLSI-SoC (2014)
Simon Pontie, Paolo Maistri, Régis Leveugle
An Elliptic Curve Crypto-Processor Secured by Randomized Windows. DSD (2014)
Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC (2014)
Simon Pontie, Paolo Maistri
Randomized windows for secure scalar multiplication on elliptic curves. ASAP (2014)
Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hély, Vincent Beroulle
On error models for RTL security evaluations. DTIS (2014)
Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) (2014)
Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. DATE (2014)
Diego Alberto, Paolo Maistri, Régis Leveugle
Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling. DTIS (2014)
Diego Alberto, Paolo Maistri, Régis Leveugle
Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems. Inf. Secur. J. A Glob. Perspect. 22 (5-6) (2013)
Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle
An evaluation of an AES implementation protected against EM analysis. ACM Great Lakes Symposium on VLSI (2013)
Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle
Countermeasures against EM analysis for a secured FPGA-based AES implementation. ReConFig (2013)
Paolo Maistri
Countermeasures against fault attacks: The good, the bad, and the ugly. IOLTS (2011)
Paolo Maistri, Régis Leveugle
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD (2011)
Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24 (2) (2011)
Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP (2010)
Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert
Statistical fault injection: Quantified error and confidence. DATE (2009)
Paolo Maistri, Régis Leveugle
Towards automated fault pruning with Petri Nets. IOLTS (2009)
Paolo Maistri
Pruning single event upset faults with petri nets. LATW (2009)
Paolo Maistri, Cyril Excoffon, Régis Leveugle
Software BIST capabilities of a symmetric cipher. ICECS (2008)
Paolo Maistri, Cyril Excoffon, Régis Leveugle
Software Self-Testing of a Symmetric Cipher with Error Detection Capability. IOLTS (2008)
Paolo Maistri, Régis Leveugle
Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers 57 (11) (2008)
Luca Breveglieri, Israel Koren, Paolo Maistri
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers. IEEE Trans. Computers 56 (5) (2007)
Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT (2007)
Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC (2007)
Luca Breveglieri, Israel Koren, Paolo Maistri
A Fault Attack Against the FOX Cipher Family. FDTC (2006)
Luca Breveglieri, Paolo Maistri, Israel Koren
A Note on Error Detection in an RSA Architecture by Means of Residue Codes. IOLTS (2006)
Luca Breveglieri, Israel Koren, Paolo Maistri, M. Ravasio
Incorporating Error Detection in an RSA Architecture. FDTC (2006)
Luca Breveglieri, Israel Koren, Paolo Maistri
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. DFT (2005)
Luca Breveglieri, Israel Koren, Paolo Maistri
Detecting Faults in Four Symmetric Key Block Ciphers. ASAP (2004)
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost. DFT (2004)
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard. DFT (2003)
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm. ASAP (2003)
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard. IEEE Trans. Computers 52 (4) (2003)
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard. DFT (2002)
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard. ASAP (2002)