Salvador Mir

ORCID

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 39

Top Venues

Publications

Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. LATS (2023)
Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mickael Casse, Philippe Galy
Noise modeling using look-up tables and DC measurements for cryogenic applications. VLSI-SoC (2023)
Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. LATS (2023)
Ankush Mamgain, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Jai Narayan Tripathi
A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. NEWCAS (2023)
Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. ISCAS (2023)
Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragan
On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. ATS (2022)
William R. Eisenstadt, Mark Roos, Devin Morris, José Luis González-Jiménez, Christopery Mounet, Manuel J. Barragan, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière
Special Session on RF/5G Test. ETS (2022)
Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS (2022)
Manasa Madhvaraj, Salvador Mir, Manuel J. Barragan
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. VLSI-SoC (2022)
Ankush Mamgain, Manuel J. Barragan, Salvador Mir
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. ETS (2021)
Ahcène Bounceur, Salvador Mir, Reinhardt Euler, Kamel Beznia
Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (5) (2020)
Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS (2020)
Renato S. Feitoza, Manuel J. Barragan, Antonio J. Ginés, Salvador Mir
-based switching SAR ADCs using a reduced-code measurement technique. NEWCAS (2020)
Renato S. Feitoza, Manuel J. Barragan, Antonio J. Ginés, Salvador Mir
-based switching SAR ADCs using an incremental analog-to-digital converter. ETS (2020)
Guillaume Renaud, Mamadou Diallo, Manuel J. Barragan, Salvador Mir
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Renato S. Feitoza, Manuel J. Barragan, Salvador Mir
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. VLSI-SoC (2019)
Manuel J. Barragan, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir
On the use of causal feature selection in the context of machine-learning indirect test. DATE (2019)
Hani Malloug, Manuel J. Barragan, Salvador Mir
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. ETS (2019)
Florent Cilici, Gildas Léger, Manuel J. Barragan, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. SMACD (2019)
Florent Cilici, Manuel J. Barragan, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Léger
Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. ISCAS (2019)
Hani Malloug, Manuel J. Barragan, Salvador Mir
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. 34 (3) (2018)
Renato S. Feitoza, Manuel J. Barragan, Salvador Mir, Daniel Dzahini
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. IOLTS (2018)
Florent Cilici, Manuel J. Barragan, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. ETS (2018)
Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragan, Salvador Mir
Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. VTS (2017)
Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. ETS (2017)
Michele Portolan, Manuel J. Barragan, Rshdee Alhakim, Salvador Mir
Mixed-signal BIST computation offloading using IEEE 1687. ETS (2017)
Cédric Pastorelli, Pascal Mellot, Salvador Mir, Cédric Tubert
ADC Techniques for Optimized Conversion Time in CMOS Image Sensors. IMSE (2016)
Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld
Built-in test of millimeter-Wave circuits based on non-intrusive sensors. DATE (2016)
Manuel J. Barragan, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Manuel J. Barragan, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test 33 (6) (2016)
Guillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32 (4) (2016)
Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragan, Salvador Mir
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS (2016)
Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. J. Electron. Test. 31 (4) (2015)
Athanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Salvador Mir
Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors. ISVLSI (2015)
Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir
A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters. ACM Trans. Design Autom. Electr. Syst. 20 (2) (2015)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Haralampos-G. D. Stratigopoulos, Manuel J. Barragan, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC (2015)
Richun Fei, Jocelyn Moreau, Salvador Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou
Horizontal-FPN fault coverage improvement in production test of CMOS imagers. VTS (2015)
Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
High frequency jitter estimator for SoCs. ETS (2015)
Guillaume Renaud, Manuel J. Barragan, Salvador Mir, Marc Sabut
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. ATS (2014)
Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
Low-cost EVM built-in test of RF transceivers. IDT (2014)
Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos
Solutions for the self-adaptation of communicating systems in operation. IOLTS (2014)
Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo
Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. MWSCAS (2014)
Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragan
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC (2014)
Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragan
Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) (2014)
Richun Fei, Jocelyn Moreau, Salvador Mir
BIST of interconnection lines in the pixel matrix of CMOS imagers. IWASI (2013)
Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir
Efficient minimization of test frequencies for linear analog circuits. ETS (2013)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
Reduced code linearity testing of pipeline adcs in the presence of noise. VTS (2013)
Kamel Beznia, Ahcène Bounceur, Salvador Mir, Reinhardt Euler
Statistical modelling of analog circuits for test metrics computation. DTIS (2013)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
True non-intrusive sensors for RF built-in test. ITC (2013)
Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Salvador Mir, Yann Kieffer
Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods. VLSI-SoC (Selected Papers) (2013)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
Reduced-Code Linearity Testing of Pipeline ADCs. IEEE Des. Test 30 (6) (2013)
Ke Huang, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Salvador Mir, Ahcène Bounceur
Multivariate statistical techniques for analog parametric test metrics estimation. DTIS (2013)
Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir
New techniques for selecting test frequencies for linear analog circuits. VLSI-SoC (2013)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet
Defect-oriented non-intrusive RF test using on-chip temperature sensors. VTS (2013)
Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
Fault modeling and diagnosis for nanometric analog circuits. ITC (2013)
Nourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani
Analog/RF test ordering in the early stages of production testing. VTS (2012)
Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir, Camelia Hora, Yizi Xing, Bram Kruseman
Diagnosis of Local Spot Defects in Analog Circuits. IEEE Trans. Instrum. Meas. 61 (10) (2012)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet
Testing RF circuits with true non-intrusive built-in sensors. DATE (2012)
Kamel Beznia, Ahcène Bounceur, Louay Abdallah, Ke Huang, Salvador Mir, Reinhardt Euler
Accurate estimation of analog test metrics with extreme circuits. ICECS (2012)
Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. ETS (2012)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
Experiences with non-intrusive sensors for RF built-in test. ITC (2012)
Haralampos-G. D. Stratigopoulos, Salvador Mir
Adaptive Alternate Analog Test. IEEE Des. Test Comput. 29 (4) (2012)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
RF Front-End Test Using Built-in Sensors. IEEE Des. Test Comput. 28 (6) (2011)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
Implicit test of high-speed analog circuits using non-intrusive sensors. ECCTD (2011)
Alexios Spyronasios, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study. Asian Test Symposium (2011)
Ahcène Bounceur, Salvador Mir, Haralampos-G. D. Stratigopoulos
Estimation of Analog Parametric Test Metrics Using Copulas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (9) (2011)
Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni
Adaptive logical control of RF LNA performances for efficient energy consumption. VLSI-SoC (2010)
Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir
Sensors for built-in alternate RF test. ETS (2010)
Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation. Asian Test Symposium (2010)
Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni
Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption. VLSI-SoC (Selected Papers) (2010)
Gustavo P. Rehder, Salvador Mir, Libor Rufer, Emmanuel Simeu, Hoang Nam Nguyen
Low Frequency Test for RF MEMS Switches. DELTA (2010)
Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur
Density estimation for analog/RF test problem solving. VTS (2010)
Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
Defect filter for alternate RF test. ETS (2010)
Nourredine Akkouche, Salvador Mir, Emmanuel Simeu
Ordering of analog specification tests based on parametric defect level estimation. VTS (2010)
Fabio Cenni, Jeremie Cazalbou, Salvador Mir, Libor Rufer
Design of a SAW-based chemical sensor with its microelectronics front-end interface. Microelectron. J. 41 (11) (2010)
Haralampos-G. D. Stratigopoulos, Salvador Mir
Analog test metrics estimates with PPM accuracy. ICCAD (2010)
Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
Fault diagnosis of analog circuits based on machine learning. DATE (2010)
Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir
Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. ICCD (2009)
Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
Defect Filter for Alternate RF Test. ETS (2009)
Rafik Khereddine, Emmanuel Simeu, Salvador Mir
Parameter identification of RF transceiver blocks using regressive models. PDeS (2009)
Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur, Emmanuel Simeu
Pseudorandom BIST for test and characterization of linear and nonlinear MEMS. Microelectron. J. 40 (7) (2009)
Livier Lizarraga, Salvador Mir, Gilles Sicard
Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors. VTS (2009)
Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris
Enrichment of limited training sets in machine-learning-based analog/RF test. DATE (2009)
Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur
Evaluation of Analog/RF Test Measurements at the Design Stage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (4) (2009)
Emmanuel Simeu, Hoang Nam Nguyen, Philippe Cauvet, Salvador Mir, Libor Rufer, Rafik Khereddine
Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing. VLSI Design 2008 (2008)
Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. DATE (2008)
Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. J. Electron. Test. 23 (6) (2007)
Luís Rolíndez, Salvador Mir, Jean-Louis Carbonéro, Dimitri Goguet, Nabil Chouba
A stereo audio Σ∑ ADC architecture with embedded SNDR self-test. ITC (2007)
Livier Lizarraga, Salvador Mir, Gilles Sicard
Evaluation of a BIST Technique for CMOS Imagers. ATS (2007)
Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro
Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. DATE (2007)
Emmanuel Simeu, Salvador Mir, R. Kherreddine, Hoang Nam Nguyen
Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. IOLTS (2007)
Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur
Study of a BIST Technique for CMOS Active Pixel Sensors. VLSI-SoC (2006)
Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu
CAT platform for analogue and mixed-signal test evaluation and optimization. VLSI-SoC (2006)
Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro
A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting. J. Electron. Test. 22 (4-6) (2006)
Salvador Mir, Kwang-Ting (Tim) Cheng, Andrew Richardson
Guest Editorial. J. Electron. Test. 22 (4-6) (2006)
Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu
CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization. VLSI-SoC (Selected Papers) (2006)
Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro
A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. VTS (2006)
Salvador Mir, Libor Rufer, Achraf Dhayni
Built-in-self-test techniques for MEMS. Microelectron. J. 37 (12) (2006)
Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur
Pseudorandom functional BIST for linear and nonlinear MEMS. DATE (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Salvador Mir