Eduardo J. Peralías

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 16

Top Topics

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Carlos Manuel Domínguez-Matas, Antonio J. Ginés, Aránzazu Otín, Valentin Gutierrez, Gildas Léger, Eduardo J. Peralías
Behavioral Model for High-Speed SAR ADCs With On-Chip References. IEEE Trans. Very Large Scale Integr. Syst. 31 (12) (2023)
Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, C. Dominguez, Maria Angeles Jalón, L. Carranza
A Single-Event Latchup setup for high-precision AMS circuits. ETS (2023)
Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías
Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy. NEWCAS (2020)
J. A. Serrano, Antonio J. Ginés, Eduardo J. Peralías
Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential. ISCAS (2020)
Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías
Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy. ISCAS (2020)
Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías
Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL. NEWCAS (2020)
Rafaella Fiorelli, Nicolás Barabino, Fernando Silveira, Eduardo J. Peralías
Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs. Circuits Syst. Signal Process. 39 (6) (2020)
Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Mismatch and Offset Calibration in Redundant SAR ADC. DCIS (2019)
Antonio J. Ginés, Antonio Lopez-Angulo, Eduardo J. Peralías, Adoración Rueda
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. ISCAS (2018)
Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Redundant SAR ADCs with Split-capacitor DAC. ICECS (2018)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Manuel J. Barragan, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
On the limits of machine learning-based test: A calibrated mixed-signal system case study. DATE (2017)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Rafaella Fiorelli, Eduardo J. Peralías
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation. Integr. 52 (2016)
Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragan, Salvador Mir
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS (2016)
Antonio Jose Ginés, Eduardo J. Peralías, Adoración Rueda
Background Digital Calibration of Comparator Offsets in Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Juan Núñez, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. LASCAS (2015)
Eduardo J. Peralías, Antonio Jose Ginés, Adoración Rueda
INL systematic reduced-test technique for Pipeline ADCs. ETS (2014)
Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda
Closed-loop simulation method for evaluation of static offset in discrete-time comparators. ICECS (2014)
Ricardo Doldán, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Analysis of steady-state common-mode response in differential LC-VCOs. ISCAS (2012)
Antonio Jose Ginés, Alberto Villegas, Eduardo J. Peralías, Adoración Rueda
Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters. ICECS (2012)
Rafaella Fiorelli, Alberto Villegas, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS. ECCTD (2011)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus. IEEE Trans. Instrum. Meas. 60 (2) (2011)
Alberto Villegas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda
-order CMOS complex filter for IEEE 802.15.4 standard. ESSCIRC (2011)
Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
On Chopper Effects in Discrete-Time SigmaDelta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Antonio J. Ginés, Ricardo Doldán, Adoración Rueda, Eduardo J. Peralías
Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. ICECS (2010)
Maria Angeles Jalón, Eduardo J. Peralías
ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method. J. Electron. Test. 26 (1) (2010)
Rafaella Fiorelli, Eduardo J. Peralías, Nicolás Barabino, Fernando Silveira
A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow. ICECS (2010)
Antonio J. Ginés, Ricardo Doldán, Manuel J. Barragan Asian, Adoración Rueda, Eduardo J. Peralías
On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. ISCAS (2010)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
A survey on digital background calibration of ADCs. ECCTD (2009)
Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías
Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. SBCCI (2009)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation. ECCTD (2009)
Ricardo Doldán Lorenzo, Antonio Jose Ginés Arteaga, Adoración Rueda, Eduardo J. Peralías
A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology. APCCAS (2008)
Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda, José Luis Huertas
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. SBCCI (2008)
Antonio Jose Ginés, Ricardo Doldán, Alberto Villegas, Antonio J. Acosta, Maria Angeles Jalón, Diego Vázquez, Adoración Rueda, Eduardo J. Peralías
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. APCCAS (2008)
Eduardo J. Peralías, Maria Angeles Jalón, Adoración Rueda
Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach. VLSI Design 2008 (2008)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. SBCCI (2007)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Improved Background Algorithms for Pipeline ADC Full Calibration. ISCAS (2007)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. ISCAS (2006)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Full calibration digital techniques for pipeline ADCs. ISCAS (3) (2005)
Guillermo Zatorre-Navarro, Eduardo J. Peralías, Santiago Celma Pueyo, Concepción Aldea Chagoyen, Nicolás J. Medrano-Marqués
Digital self-tuning technique for continuous-time filters. ICECS (2005)
Gildas Léger, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2004)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Digital Background Gain Error Correction in Pipeline ADCs. DATE (2004)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. SBCCI (2003)
Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
Practical Oscillation-Based Test of Integrated Filters. IEEE Des. Test Comput. 19 (6) (2002)
Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. IEEE Des. Test Comput. 19 (6) (2002)
Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. DATE (2002)
Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
Analog/mixed-signal IP modeling for design reuse. DATE (2001)
Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas
Self-Testable Pipelined ADC with Low Hardware Overhead. VTS (2001)
Eduardo J. Peralías, Adoración Rueda, José L. Huertas
Structural testing of pipelined analog to digital converters. ISCAS (1) (2001)
Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. J. Electron. Test. 17 (5) (2001)
Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE (2000)
Eduardo J. Peralías, Adoración Rueda, José L. Huertas
Alternative DFT Strategies for High-Speed Pipelined Data Converters. LATW (2000)
Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS (2000)
Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. Asian Test Symposium (2000)
Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
VHDL-based behavioural description of pipeline ADCs. ISCAS (2000)
Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. DATE (1998)
Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas
DfT and on-line test of high-performance data converters: a practical case. ITC (1998)
Eduardo J. Peralías, Adoración Rueda, José L. Huertas
CMOS pipelined A/D converters with concurrent error detection capability. ICECS (1998)
Diego Vázquez, Adoración Rueda, José Luis Huertas, Eduardo J. Peralías
A high-Q bandpass fully differential SC filter with enhanced testability. IEEE J. Solid State Circuits 33 (7) (1998)
Eduardo J. Peralías, Adoración Rueda, José L. Huertas
A DFT Technique for Analog-to-Digital Converters with digital correction. VTS (1997)
Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC (1997)
Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
Statistical behavioral modeling and characterization of A/D converters. ICCAD (1995)