Juan Núñez

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 24

Top Topics

Hardware Implementation

Design Considerations

Computing Paradigms

Countermeasures

Top Venues

Int. J. Circuit Theory Appl.

Publications

Jose M. Gata-Romero, Elisenda Roca, Juan Núñez, Rafael Castro-López, Francisco V. Fernández
Reliability evaluation of IC Ring Oscillator PUFs. SMACD (2023)
Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez, Rafael Castro-López, Elisenda Roca, Hussam Amrouch
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. IRPS (2023)
Maria J. Avedillo, Manuel Jiménez Través, Corentin Delacour, Aida Todri-Sanial, Bernabé Linares-Barranco, Juan Núñez
Operating Coupled VO₂-Based Oscillators for Solving Ising Models. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (4) (2023)
Juan Núñez, Maria J. Avedillo, Manuel Jiménez
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. SMACD (2023)
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embed. Syst. Lett. 14 (2) (2022)
Juan Núñez, Simon Thomann, Hussam Amrouch, Maria J. Avedillo
Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. ICECS 2022 (2022)
Manuel Jiménez, Maria José Avedillo, Juan Núñez, Bernabé Linares-Barranco
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. DCIS (2022)
Aida Todri-Sanial, Stefania Carapezzi, Corentin Delacour, Madeleine Abernot, Thierry Gil, Elisabetta Corti, Siegfried F. Karg, Juan Núñez, Manuel Jiménez, Maria J. Avedillo, Bernabé Linares-Barranco
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Trans. Neural Networks Learn. Syst. 33 (5) (2022)
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Juan Núñez, José M. Quintana, Maria José Avedillo, Manuel Jiménez, Aida Todri-Sanial, Elisabetta Corti, Siegfried F. Karg, Bernabé Linares-Barranco
Oscillators for ONNs. IEEE Trans. Circuits Syst. II Express Briefs 68 (10) (2021)
Manuel Jiménez, Juan Núñez, Maria José Avedillo
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. ISCAS (2020)
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. ACM J. Emerg. Technol. Comput. Syst. 16 (3) (2020)
Juan Núñez, Maria J. Avedillo
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access 7 (2019)
Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
Experimental Characterization of Time-Dependent Variability in Ring Oscillators. SMACD (2019)
Aida Todri-Sanial, Xueqing Li, Juan Núñez
Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications. Int. J. Circuit Theory Appl. 47 (9) (2019)
Pablo Martín-Lloret, Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. SMACD (2019)
Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. DCIS (2018)
Rafaella Fiorelli, Juan Núñez, Fernando Silveira
All-inversion region gm/ID methodology for RF circuits in FinFET technologies. NEWCAS (2018)
Pablo Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, Juan Núñez, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. SMACD (2018)
Hector J. Quintero, Manuel Jimenez, Maria J. Avedillo, Juan Núñez
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. SMACD (2018)
Maria J. Avedillo, Juan Núñez
Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Int. J. Circuit Theory Appl. 46 (3) (2018)
Juan Núñez, Maria J. Avedillo
Exploring logic architectures suitable for TFETs devices. ISCAS (2017)
Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez
Secure cryptographic hardware implementation issues for high-performance applications. PATMOS (2016)
Maria J. Avedillo, Juan Núñez
Impact of pipeline in the power performance of tunnel transistor circuits. PATMOS (2016)
Juan Núñez, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. LASCAS (2015)
Juan Núñez, Maria J. Avedillo, Hector J. Quintero
DOE based high-performance gate-level pipelines. PATMOS (2014)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. DSD (2013)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Novel pipeline architectures based on Negative Differential Resistance devices. Microelectron. J. 44 (9) (2013)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Compact and Power Efficient MOS-NDR Muller C-Elements. DoCEIS (2012)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Bifurcation diagrams in MOS-NDR frequency divider circuits. ICECS (2012)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. PATMOS (2012)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Efficient realization of RTD-CMOS logic gates. ACM Great Lakes Symposium on VLSI (2011)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Single phase MOS-NDR mobile networks. ISCAS (2010)
Juan Núñez, Maria J. Avedillo, José M. Quintana
Evaluation of RTD-CMOS Logic Gates. DSD (2010)
José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi
Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. ISCAS (2009)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Limits to a correct operation in RTD-based ternary inverters. ISCAS (2008)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Correct operation in SMOBILE-based quasi-differential quantizers. ECCTD (2007)
Juan Núñez, José M. Quintana, Maria J. Avedillo
A quasi-differential quantizer based on SMOBILE. SBCCI (2007)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI (2007)
Juan Núñez, José M. Quintana, Maria J. Avedillo
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL (2007)
José M. Quintana, Maria J. Avedillo, Juan Núñez
Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD (2006)
Juan Núñez, José M. Quintana, Maria José Avedillo
Limits to a Correct Evaluation in RTD-based Ternary Inverters. ICECS (2006)