Antonio J. Acosta

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 13

Top Topics

Countermeasures

Hardware Implementation

Top Venues

Int. J. Circuit Theory Appl.

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Virginia Zúñiga-González, Erica Tena-Sánchez, Antonio J. Acosta
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks. DCIS (2023)
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. ACM J. Emerg. Technol. Comput. Syst. 16 (3) (2020)
Erica Tena-Sánchez, Antonio J. Acosta
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. Int. J. Circuit Theory Appl. 47 (2) (2019)
Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. DCIS (2018)
Erica Tena-Sánchez, Antonio J. Acosta
Effect of Temperature Variation in Experimental DPA and DEMA Attacks. PATMOS (2018)
Antonio J. Acosta, Tommaso Addabbo, Erica Tena-Sánchez
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. Int. J. Circuit Theory Appl. 45 (2) (2017)
Antonio J. Acosta, Tommaso Addabbo
Guest Editorial "Secure lightweight crypto-hardware". Int. J. Circuit Theory Appl. 45 (2) (2017)
Antonio J. Acosta, Erica Tena-Sánchez, Carlos Jesús Jiménez-Fernández, Javier M. Mora-Merchan
Power and Energy Issues on Lightweight Cryptography. J. Low Power Electron. 13 (3) (2017)
Piedad Brox, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Iluminada Baturone, Antonio J. Acosta
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. Int. J. Circuit Theory Appl. 44 (1) (2016)
Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez
Secure cryptographic hardware implementation issues for high-performance applications. PATMOS (2016)
Erica Tena-Sánchez, Antonio J. Acosta
DPA vulnerability analysis on Trivium stream cipher using an optimized power model. ISCAS (2015)
Macarena C. Martínez-Rodríguez, Piedad Brox, Erica Tena, Antonio J. Acosta, Iluminada Baturone
Programmable ASICs for model predictive control. ICIT (2015)
Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. PATMOS (2014)
Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (2) (2014)
Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
Low-Power Differential Logic Gates for DPA Resistant Circuits. DSD (2014)
Piedad Brox, Javier Castro-Ramirez, Macarena C. Martínez-Rodríguez, Erica Tena, Carlos Jesús Jiménez-Fernández, Iluminada Baturone, Antonio J. Acosta
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2013)
Macarena C. Martínez-Rodríguez, Piedad Brox, Javier Castro-Ramirez, Erica Tena, Antonio J. Acosta, Iluminada Baturone
ASIC-in-the-loop methodology for verification of piecewise affine controllers. ICECS (2012)
Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS (2010)
Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS (2009)
Antonio Jose Ginés, Ricardo Doldán, Alberto Villegas, Antonio J. Acosta, Maria Angeles Jalón, Diego Vázquez, Adoración Rueda, Eduardo J. Peralías
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. APCCAS (2008)
Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
Asymmetric clock driver for improved power and noise performances. ISCAS (2007)
Renato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider
Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. ISCAS (2007)
Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD (2007)
Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta
Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS (2006)
Manuel Delgado-Restituto, Antonio J. Acosta, Ángel Rodríguez-Vázquez
A mixed-signal integrated circuit for FM-DCSK modulation. IEEE J. Solid State Circuits 40 (7) (2005)
Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. 1 (1) (2005)
Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS (2003)
Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS (2002)
Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS (2002)
Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
Analog/mixed-signal IP modeling for design reuse. DATE (2001)
Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) (2001)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE (2001)
Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE (2000)
Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS (2000)
Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
Inertial and degradation delay model for CMOS logic gates. ISCAS (2000)
Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS (2000)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Degradation Delay Model Extension to CMOS Gates. PATMOS (2000)
Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
VHDL-based behavioural description of pipeline ADCs. ISCAS (2000)
T. A. García, Antonio J. Acosta, J. M. Mora, J. Ramos, José Luis Huertas
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. J. Electron. Test. 15 (1-2) (1999)
Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia
Efficient self-timed circuits based on weak NMOS-trees. ICECS (1998)
T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. VTS (1998)
Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas
New CMOS VLSI linear self-timed architectures. ASYNC (1995)
Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44 (12) (1995)
Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS (1993)
Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas
Modeling of real bistables in VHDL. EURO-DAC (1993)