Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.

Pilar Parra Fernández Antonio J. Acosta Manuel Valencia-Barrero

Published in: PATMOS (2002)

Keyphrases

low power
power consumption
power reduction
low power consumption
power dissipation
low cost
high speed
single chip
digital signal processing
logic circuits
energy efficiency
noise model
vlsi architecture
signal to noise ratio
image sensor
energy saving
cmos technology
power saving
data center
vlsi circuits
gate array