Pilar Parra Fernández

Publication Activity (10 Years)

Years Active: 2002-2020
Publications (10 Years): 3

Top Topics

Efficient Implementation

Electronic Circuits

Top Venues

Rev. Iberoam. de Tecnol. del Aprendiz.

Publications

Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández
Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors 20 (23) (2020)
Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero
An Academic Approach to FPGA Design Based on a Distance Meter Circuit. Rev. Iberoam. de Tecnol. del Aprendiz. 15 (3) (2020)
Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. DCIS (2018)
Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS (2010)
Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS (2009)
Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
Asymmetric clock driver for improved power and noise performances. ISCAS (2007)
Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD (2007)
Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta
Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS (2006)
Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. 1 (1) (2005)
Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS (2003)
Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS (2002)
Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS (2002)