Login / Signup
Selective Clock-Gating for Low-Power Synchronous Counters.
Pilar Parra Fernández
Antonio J. Acosta
Raúl Jiménez
Manuel Valencia-Barrero
Published in:
J. Low Power Electron. (2005)
Keyphrases
</>
low power
power consumption
power reduction
power dissipation
high speed
low cost
single chip
low power consumption
power management
power saving
digital signal processing
cmos technology
data center
logic circuits
vlsi architecture
energy saving
image sensor
vlsi circuits