Manuel Valencia-Barrero

Publication Activity (10 Years)

Years Active: 1986-2021
Publications (10 Years): 11

Top Topics

Power Reduction

Fault Detection

Countermeasures

Fpga Implementation

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Rev. Iberoam. de Tecnol. del Aprendiz.

Publications

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. IEEE Access 9 (2021)
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. Sensors 21 (22) (2021)
Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández
Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors 20 (23) (2020)
José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. IEEE Trans. Circuits Syst. (11) (2020)
Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, R. Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. ISCAS (2020)
Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero
An Academic Approach to FPGA Design Based on a Distance Meter Circuit. Rev. Iberoam. de Tecnol. del Aprendiz. 15 (3) (2020)
Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. DCIS (2018)
José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
Trivium hardware implementations for power reduction. Int. J. Circuit Theory Appl. 45 (2) (2017)
José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
Multiradix Trivium Implementations for Low-Power IoT Hardware. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
Vulnerability Analysis of Trivium FPGA Implementations. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
Fault attack on FPGA implementations of Trivium stream cipher. ISCAS (2016)
José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
Low Power Implementation of Trivium Stream Cipher. PATMOS (2012)
Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
Asymmetric clock driver for improved power and noise performances. ISCAS (2007)
Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD (2007)
Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. 1 (1) (2005)
Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS (2002)
Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) (2001)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE (2001)
Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS (2000)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Degradation Delay Model Extension to CMOS Gates. PATMOS (2000)
Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas
New CMOS VLSI linear self-timed architectures. ASYNC (1995)
Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44 (12) (1995)
Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS (1993)
Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas
Modeling of real bistables in VHDL. EURO-DAC (1993)
J. Calvo, José I. Acha, Manuel Valencia-Barrero
Asynchronous Modular Arbiter. IEEE Trans. Computers 35 (1) (1986)