Jorge Juan-Chico

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 4

Top Topics

Functional Verification

Basis Functions

Top Venues

Microprocess. Microsystems

EURASIP J. Adv. Signal Process.

Internet Things

Publications

German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Julian Viejo-Cortes
IRIS: An embedded secure boot for IoT devices. Internet Things 23 (2023)
German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel Jesús Bellido Díaz, David Guerrero Martos, Julian Viejo-Cortes, Jorge Juan-Chico
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. IEEE Access 9 (2021)
David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020 (1) (2020)
David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Address-encoded byte order. Microprocess. Microsystems 78 (2020)
David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS (2007)
David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3 (1) (2007)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2 (1) (2006)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS (2005)
Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS (2005)
Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS (2004)
David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS (2003)
Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium (2003)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS (2002)
Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS (2002)
Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS (2002)
Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) (2001)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE (2001)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
AUTODDM: automatic characterization tool for the delay degradation model. ICECS (2001)
Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS (2000)
Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
Inertial and degradation delay model for CMOS logic gates. ISCAS (2000)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Degradation Delay Model Extension to CMOS Gates. PATMOS (2000)