Manuel Jesús Bellido Díaz

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 4

Top Topics

Functional Verification

Computing Power

Top Venues

Microelectron. J.

EURASIP J. Adv. Signal Process.

Internet Things

Publications

German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Julian Viejo-Cortes
IRIS: An embedded secure boot for IoT devices. Internet Things 23 (2023)
German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel Jesús Bellido Díaz, David Guerrero Martos, Julian Viejo-Cortes, Jorge Juan-Chico
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. IEEE Access 9 (2021)
David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020 (1) (2020)
Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos
Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. 67 (2017)
Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. 60 (12) (2011)
Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa
Design and implementation of a suitable core for on-chip long-term verification. SIES (2010)
David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3 (1) (2007)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2 (1) (2006)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS (2005)
Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS (2005)