Paulino Ruiz-de-Clavijo

Publication Activity (10 Years)

Years Active: 2000-2020
Publications (10 Years): 4

Top Topics

Euclidean Distance

Computational Power

Network Security

Software Implementation

Top Venues

Microelectron. J.

Microprocess. Microsystems

EURASIP J. Adv. Signal Process.

Publications

David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020 (1) (2020)
David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Address-encoded byte order. Microprocess. Microsystems 78 (2020)
Alejandro Carrasco, Jorge Ropero, Paulino Ruiz-de-Clavijo, Jaime Benjumea, Amalia Luque
A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot. QRS Companion (2018)
Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos
Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. 67 (2017)
David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7 (3) (2011)
Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. 60 (12) (2011)
Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. 6 (1) (2010)
Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS (2008)
Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES (2007)
David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS (2007)
David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3 (1) (2007)
Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES (2006)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2 (1) (2006)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS (2005)
Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS (2005)
Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS (2004)
David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS (2003)
Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium (2003)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS (2002)
Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS (2002)
Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS (2002)
Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) (2001)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE (2001)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
AUTODDM: automatic characterization tool for the delay degradation model. ICECS (2001)
Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
Inertial and degradation delay model for CMOS logic gates. ISCAS (2000)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Degradation Delay Model Extension to CMOS Gates. PATMOS (2000)