Manuel J. Bellido

Publication Activity (10 Years)

Years Active: 1993-2020
Publications (10 Years): 2

Top Topics

Image Sequences

Genetic Algorithm

Complex Systems

Top Venues

Comput. Informatics

Microprocess. Microsystems

Publications

David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Address-encoded byte order. Microprocess. Microsystems 78 (2020)
Juan Quiros, Sergey Verlan, Julian Viejo, Alejandro Millán, Manuel J. Bellido
Fast Hardware Implementations of Static P Systems. Comput. Informatics 35 (3) (2016)
Jorge Juan, Julian Viejo, Manuel J. Bellido
Network Time Synchronization: A Full Hardware Approach. PATMOS (2012)
David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7 (3) (2011)
Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. 6 (1) (2010)
J. I. Villar, Jorge Juan, Manuel J. Bellido
Efficient techniques and methodologies for embedded system design usign free hardware and open standards. FPL (2009)
Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS (2008)
Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES (2007)
David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS (2007)
Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES (2006)
Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS (2004)
David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS (2003)
Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium (2003)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS (2002)
Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS (2002)
Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS (2002)
Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) (2001)
Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE (2001)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
AUTODDM: automatic characterization tool for the delay degradation model. ICECS (2001)
Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS (2000)
Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
Inertial and degradation delay model for CMOS logic gates. ISCAS (2000)
Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
Degradation Delay Model Extension to CMOS Gates. PATMOS (2000)
Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia
Efficient self-timed circuits based on weak NMOS-trees. ICECS (1998)
P. Fortet, Manuel J. Bellido, Francisco Sivianes, A. V. Medina
Multimedia System for Instruction and Learning Electronics. CALISCE (1996)
Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas
SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits 30 (7) (1995)
Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas
New CMOS VLSI linear self-timed architectures. ASYNC (1995)
Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44 (12) (1995)
Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS (1993)
Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas
Modeling of real bistables in VHDL. EURO-DAC (1993)