EURO-DAC

Keyphrases

Publications

1996

Michael Gschwind, Dietmar Maurer
An extendable MIPS-I processor kernel in VHDL for hardware/software co-design. EURO-DAC (1996)
Dirk Rabe, Wolfgang Nebel
New approach in gate-level glitch modelling. EURO-DAC (1996)
Matthias A. Senn, Peter H. Schneider, Bernd Wurth
Power analysis for sequential circuits at logic level. EURO-DAC (1996)
Sabih H. Gerez, Erwin G. Woutersen
Assignment of storage values to sequential read-write memories. EURO-DAC (1996)
Zeljko Mrcarica, Helmut Detter, D. Glozic, Vanco B. Litovski
Describing space-continuous models of microelectromechanical devices for behavioral simulation. EURO-DAC (1996)
Tobias H. Abthoff, Frank M. Johannes
TINA: analog placement using enumerative techniques capable of optimizing both area and net length. EURO-DAC (1996)
Konrad Feyerabend, Rainer Schlör
Hardware synthesis from requirement specifications. EURO-DAC (1996)
Massoud Pedram, Jui-Ming Chang
Module assignment for low power. EURO-DAC (1996)
Francesco Curatelli, Marco Chirico, Leonardo Mangeruca
Specification and management of timing constraints in behavioral VHDL. EURO-DAC (1996)
T. Murayama, Yuji Gendai
A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL. EURO-DAC (1996)
Christoph Grimm, Klaus Waldschmidt
KIR - a graph-based model for description of mixed analog/digital systems. EURO-DAC (1996)
Georg Pelz, Jürgen Bielefeld, Günther Hess, Günter Zimmer
Hardware/software-cosimulation for mechatronic system design. EURO-DAC (1996)
C.-J. Richard Shi
Entity overloading for mixed-signal abstraction in VHDL. EURO-DAC (1996)
Enrico Macii, Massimo Poncino, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
BDD-based testability estimation of VHDL designs. EURO-DAC (1996)
Paolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment. EURO-DAC (1996)
Valentina Salapura, Volker Hamann
Implementing fuzzy control systems using VHDL and statecharts. EURO-DAC (1996)
Stefano Quer, Gianpiero Cabodi, Paolo Camurati
Decomposed symbolic forward traversals of large finite state machines. EURO-DAC (1996)
Bogdan G. Arsintescu, Sorin A. Spânoche
Global stacking for analog circuits. EURO-DAC (1996)
Jürgen Bortolazzi, Thomas Hirth, Thomas Raith
Specification and design of electronic control units. EURO-DAC (1996)
Youn-Long Lin, Tsung-Yi Wu
Storage optimization by replacing some flip-flops with latches. EURO-DAC (1996)
Ekambaram Balaji, Prabhu Krishnamurthy
Modeling ASIC memories in VHDL. EURO-DAC (1996)
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich
Incremental re-encoding for symbolic traversal of product machines. EURO-DAC (1996)
Mitsuho Seki, Kazuo Kato, S. Kobayashi, Kouki Tsurusaki
A practical clock router that accounts for the capacitance derived from parallel and cross segments. EURO-DAC (1996)
Stefan Höreth
Compilation of optimized OBDD-algorithms. EURO-DAC (1996)
Vladimir A. Shepelev, Stephen W. Director
Automatic workflow generation. EURO-DAC (1996)
Wendell C. Baker, A. Richard Newton
The maximal VHDL subset with a cycle-level abstraction. EURO-DAC (1996)
Rhodri M. Davies, John V. Woods
Timing verification for asynchronous design. EURO-DAC (1996)
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
Testable path delay fault cover for sequential circuits. EURO-DAC (1996)
D. Gareth Evans, Peter N. Green, Derrick Morris
An integrated approach to engineering computer systems. EURO-DAC (1996)
Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser
A new concept for accurate modeling of VLSI interconnections and its application for timing simulation. EURO-DAC (1996)
Franz J. Rammig
Beyond VHDL: textual formalisms, visual techniques, or both? EURO-DAC (1996)
Peter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín
A refinement calculus for VHDL. EURO-DAC (1996)
Ulrich Bretthauer, Ernst-Helmut Horneber
BRASIL: the Braunschweig mixed-mode-simulator for integrated circuits. EURO-DAC (1996)
Andrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe
A system for compiling and debugging structured data processing controllers. EURO-DAC (1996)
Gunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder
A VHDL reuse workbench. EURO-DAC (1996)
Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. EURO-DAC (1996)
Maher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza, Luci Pirmez
Analysis of different protocol description styles in VHDL for high-level synthesis. EURO-DAC (1996)
Arno Kunzmann
Efficient random testing with global weights. EURO-DAC (1996)
Ayman M. Wahba, Dominique Borrione
Automatic diagnosis may replace simulation for correcting simple design errors. EURO-DAC (1996)
Eduardo de la Torre, J. Calvo, Javier Uceda
Model generation of test logic for macrocell based designs. EURO-DAC (1996)
Vladimir B. Dmitriev-Zdorov
Generalized coupling as a way to improve the convergence in relaxation-based solvers. EURO-DAC (1996)
Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo
Timing optimization by an improved redundancy addition and removal technique. EURO-DAC (1996)
Andreas Hett, Bernd Becker, Rolf Drechsler
MORE: an alternative implementation of BDD packages by multi-operand synthesis. EURO-DAC (1996)
Kenneth Y. Yun
Automatic synthesis of extended burst-mode circuits using generalized C-elements. EURO-DAC (1996)
Peter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun
A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits. EURO-DAC (1996)
Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996 EURO-DAC (1996)
Yankin Tanurhan, H. Gölz, Stefan Schmerler, Klaus D. Müller-Glaser
An approach for integrated specification and design of real-time systems. EURO-DAC (1996)
Markus Schwiegershausen, Holger Kropp, Peter Pirsch
A system level HW/SW partitioning and optimization tool. EURO-DAC (1996)
Mona M. Ahmed, Hani F. Ragaie, Hisham Haddara
A hierarchical approach to analog behavioral modeling of neural networks using HDL-A. EURO-DAC (1996)
Claus Schneider, Wolfgang Ecker
Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality. EURO-DAC (1996)