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A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
Erica Tena-Sánchez
Javier Castro-Ramirez
Antonio J. Acosta
Published in:
IEEE J. Emerg. Sel. Topics Circuits Syst. (2014)
Keyphrases
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logic circuits
logic synthesis
digital circuits
chip design
low power
delay insensitive
neural network
design methodology
high level synthesis
circuit design
countermeasures
engineering design
conceptual framework
conceptual model
software architecture
description logics
case study