Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.

T. A. García Antonio J. Acosta J. M. Mora J. Ramos José Luis Huertas

Published in: J. Electron. Test. (1999)

Keyphrases

low cost
high speed
high bandwidth
low power
neural network
statistical significance
analog vlsi
database
power consumption
statistical tests
scan data
ultra low power