Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications.

Erica Tena-Sánchez Javier Castro-Ramirez Antonio J. Acosta

Published in: PATMOS (2014)

Keyphrases

low power
cmos technology
nm technology
single chip
power consumption
high speed
low cost
logic circuits
low power consumption
power dissipation
power reduction
digital signal processing
vlsi architecture
mixed signal
wireless transmission
vlsi circuits
gate array
low voltage
delay insensitive
hardware and software