Maria José Avedillo

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 7

Top Topics

Multilayer Perceptron

Associative Memory

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jafar Shamsi, Maria José Avedillo, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
Effect of Device Mismatches in Differential Oscillatory Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Jafar Shamsi, Maria José Avedillo, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
Effect of Device Mismatches in Differential Oscillatory Neural Networks. CoRR (2022)
Manuel Jiménez, Maria José Avedillo, Juan Núñez, Bernabé Linares-Barranco
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. DCIS (2022)
Madeleine Abernot, Thierry Gil, Evgenii Kurylin, Tanguy Hardelin, Alexandre Magueresse, Théophile Gonos, Manuel Jimenez, Maria José Avedillo, Aida Todri-Sanial
Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4. IJCNN (2022)
Juan Núñez, José M. Quintana, Maria José Avedillo, Manuel Jiménez, Aida Todri-Sanial, Elisabetta Corti, Siegfried F. Karg, Bernabé Linares-Barranco
Oscillators for ONNs. IEEE Trans. Circuits Syst. II Express Briefs 68 (10) (2021)
Manuel Jiménez, Juan Núñez, Maria José Avedillo
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. ISCAS (2020)
Jafar Shamsi, Maria José Avedillo, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks. DCIS (2020)
David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS (2006)
Juan Núñez, José M. Quintana, Maria José Avedillo
Limits to a Correct Evaluation in RTD-based Ternary Inverters. ICECS (2006)
Manuel Martínez, Maria José Avedillo, José M. Quintana, José Luis Huertas
COPAS: A New Algorithm for the Partial Input Encoding Problem. VLSI Design 2002 (2) (2002)