David Bol

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 77

Top Venues

CoRR

ISCAS

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Martin Lefebvre, David Bol
A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. CICC (2024)
Martin Lefebvre, David Bol
A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-μm Bulk and 22-nm FD-SOI. CoRR (2024)
Martin Lefebvre, David Bol
A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-μm Bulk and 22-nm FD-SOI. CoRR (2024)
Ludmila Courtillat-Piazza, Thibault Pirson, Louis Golard, David Bol
A Cradle-to-Gate Life Cycle Analysis of Bitcoin Mining Equipment Using Sphera LCA and ecoinvent Databases. CoRR (2024)
Marco Gonzalez, Pol Maistriaux, David Bol
A Narrowband RF Front End in 22-nm FD-SOI Featuring a Programmable Low-Noise Amplifier with a Configurable Noise-Power Trade-Off. ISCAS (2024)
Rémi Dekimpe, David Bol
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Martin Lefebvre, Denis Flandre, David Bol
A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. CoRR (2023)
Mathieu Xhonneux, Jérôme Louveaux, David Bol
A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios. IEEE Open J. Circuits Syst. 4 (2023)
Pengcheng Xu, Denis Flandre, David Bol
Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Adrian Kneip, David Bol
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (3) (2023)
Maxime Schramme, David Bol
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (6) (2023)
Marco Gonzalez, Pengcheng Xu, Rémi Dekimpe, Maxime Schramme, Ivan Stupia, Thibault Pirson, David Bol
Technical and Ecological Limits of 2.45-GHz Wireless Power Transfer for Battery-Less Sensors. IEEE Internet Things J. 10 (17) (2023)
Charlotte Frenkel, David Bol, Giacomo Indiveri
Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence. Proc. IEEE 111 (6) (2023)
Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
CIM-SRAM With Multi-Bit Analog Batch-Normalization. IEEE J. Solid State Circuits 58 (7) (2023)
Louis Golard, Jérôme Louveaux, David Bol
Evaluation and projection of 4G and 5G RAN energy footprints: the case of Belgium for 2020-2025. Ann. des Télécommunications 78 (5-6) (2023)
Marco Gonzalez, David Bol
Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW. DATE (2023)
Martin Lefebvre, Denis Flandre, David Bol
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. IEEE J. Solid State Circuits 58 (8) (2023)
Léopold Van Brandt, Roghayeh Saeidi, David Bol, Denis Flandre
Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Martin Lefebvre, David Bol
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization. ESSCIRC (2022)
Rémi Dekimpe, David Bol
ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller. IEEE Trans. Biomed. Circuits Syst. 16 (3) (2022)
Rémi Dekimpe, David Bol
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End. ESSCIRC (2022)
Pol Maistriaux, Thibault Pirson, Maxime Schramme, Jérôme Louveaux, David Bol
Modeling the Carbon Footprint of Battery-Powered IoT Sensor Nodes for Environmental-Monitoring Applications. IOT (2022)
Martin Lefebvre, Denis Flandre, David Bol
A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI. ESSCIRC (2022)
Martin Lefebvre, David Bol
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm with 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs. CoRR (2022)
Gauthier Roussilhe, Thibault Pirson, Mathieu Xhonneux, David Bol
From Silicon Shield to Carbon Lock-in ? The Environmental Footprint of Electronic Components Manufacturing in Taiwan (2015-2020). CoRR (2022)
Mathieu Xhonneux, Orion Afisiadis, David Bol, Jérôme Louveaux
A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets. IEEE Internet Things J. 9 (5) (2022)
Thibault Pirson, Thibault P. Delhaye, Alex Pip, Grégoire Le Brun, Jean-Pierre Raskin, David Bol
The Environmental Footprint of IC Production: Meta-Analysis and Historical Trends. ESSDERC (2022)
Maxime Schramme, Léopold Van Brandt, Denis Flandre, David Bol
Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (5) (2022)
Pengcheng Xu, Denis Flandre, David Bol
A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform. IEEE J. Solid State Circuits 56 (6) (2021)
David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits 56 (7) (2021)
Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits (2021)
Thibault Pirson, David Bol
Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach. CoRR (2021)
Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC (2021)
David Bol, Thibault Pirson, Rémi Dekimpe
Moore's Law and ICT Innovation in the Anthropocene. DATE (2021)
Charlotte Frenkel, David Bol, Giacomo Indiveri
Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence. CoRR (2021)
Mathieu Xhonneux, Joachim Tapparel, Péter Scheepers, Orion Afisiadis, Alexios Balatsoukas-Stimming, David Bol, Jérôme Louveaux, Andreas Burg
A Two-User Successive Interference Cancellation LoRa Receiver with Soft-Decoding. ACSCC (2021)
Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. ISSCC (2021)
Adrian Kneip, David Bol
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (5) (2021)
Rémi Dekimpe, David Bol
A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68 (7) (2021)
Joachim Tapparel, Mathieu Xhonneux, David Bol, Jérôme Louveaux, Andreas Burg
Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers. IEEE Open J. Commun. Soc. 2 (2021)
Mathieu Xhonneux, Jérôme Louveaux, David Bol
Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller. SiPS (2021)
Itamar Levi, Davide Bellizia, David Bol, François-Xavier Standaert
Ask Less, Get More: Side-Channel Signal Hiding, Revisited. IEEE Trans. Circuits Syst. (12) (2020)
Charlotte Frenkel, Jean-Didier Legat, David Bol
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. CoRR (2020)
Charlotte Frenkel, Jean-Didier Legat, David Bol
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. ISCAS (2020)
Pengcheng Xu, Denis Flandre, David Bol
Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors. IEEE J. Solid State Circuits 54 (10) (2019)
Charlotte Frenkel, Jean-Didier Legat, David Bol
Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning. IEEE Trans. Biomed. Circuits Syst. 13 (5) (2019)
Charlotte Frenkel, Jean-Didier Legat, David Bol
Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. CoRR (2019)
Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Pierre Gérard, Denis Flandre, David Bol
A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer. Integr. 67 (2019)
Charlotte Frenkel, Martin Lefebvre, David Bol
Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training. CoRR (2019)
Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, David Bol
12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS. IEEE Trans. Biomed. Circuits Syst. 13 (1) (2019)
Ludovic Moreau, Rémi Dekimpe, David Bol
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ISCAS (2019)
Charlotte Frenkel, Jean-Didier Legat, David Bol
Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. ISCAS (2019)
David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. ISSCC (2019)
Javier Aguirre, David Bol, Denis Flandre, Carlos Sánchez-Azqueta, Santiago Celma
A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks. IEEE Trans. Ind. Electron. 65 (2) (2018)
Cecilia Gimeno, David Bol, Denis Flandre
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Remi Dekimpe, Pengcheng Xu, Maxime Schramme, Denis Flandre, David Bol
A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. PATMOS (2018)
Pengcheng Xu, Denis Flandre, David Bol
Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. A-SSCC (2018)
Cecilia Gimeno, Denis Flandre, David Bol
Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI. LASCAS (2018)
Charlotte Frenkel, Jean-Didier Legat, David Bol
9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS. CoRR (2018)
François Stas, David Bol
A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Thomas Haine, Johan Segers, Denis Flandre, David Bol
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. DATE (2018)
Dina Kamel, Davide Bellizia, François-Xavier Standaert, Denis Flandre, David Bol
Demonstrating an LPPN Processor. ASHES@CCS (2018)
Cecilia Gimeno, Denis Flandre, David Bol
Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
François Stas, David Bol
A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS. ISCAS (2017)
Charlotte Frenkel, Jean-Didier Legat, David Bol
A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors. BioCAS (2017)
François Stas, David Bol
Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. ISCAS (2017)
Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. ISCAS (2017)
Guerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, Andreia Cathelin, David Bol
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. IEEE J. Solid State Circuits 52 (4) (2017)
Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
Architecture exploration of a fixed point computation unit using precise timing spiking neurons. PATMOS (2017)
Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. ESSCIRC (2017)
Guerric de Streel, François Stas, Thibaut Gurne, François Durant, Charlotte Frenkel, David Bol
SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape. VLSI Circuits (2016)
Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. 57 (2016)
Dina Kamel, Guerric de Streel, Santos Merino Del Pozo, Kashif Nawaz, François-Xavier Standaert, Denis Flandre, David Bol
Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers. SPACE (2016)
François Stas, Guerric de Streel, David Bol
Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools. NEWCAS (2016)
Charlotte Frenkel, Jean-Didier Legat, David Bol
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. VLSI-SoC (2016)
Thomas Haine, François Stas, Guerric de Streel, Cecilia Gimeno, Denis Flandre, David Bol
CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. ICDSC (2016)
Charlotte Frenkel, Jean-Didier Legat, David Bol
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. ReCoSoC (2015)
Numa Couniot, David Bol, Olivier Poncelet, Laurent A. Francis, Denis Flandre
A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz. IEEE Trans. Circuits Syst. II Express Briefs (2) (2015)
Ahmed T. Elthakeb, Thomas Haine, Denis Flandre, Yehea Ismail, Hamdy Abd Elhamid, David Bol
Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. ISCAS (2015)
Numa Couniot, Guerric de Streel, François Botman, Angelo Kuti Lusala, Denis Flandre, David Bol
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. IEEE J. Solid State Circuits 50 (10) (2015)
Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC (2015)
David Bol, El Hafed Boufouss, Denis Flandre, Julien De Vos
5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage. ESSCIRC (2015)
Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. 10 (1) (2014)
François Botman, David Bol, Jean-Didier Legat, Kaushik Roy
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
David Bol, Guerric de Streel, François Botman, Angelo Kuti Lusala, Numa Couniot
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range. VLSIC (2014)
Julien De Vos, Denis Flandre, David Bol
A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
François Botman, Julien De Vos, Sebastien Bernard, François Stas, Jean-Didier Legat, David Bol
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. ISCAS (2014)
Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren
A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks. IEEE Trans. Emerg. Top. Comput. 2 (2) (2014)
Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS (2014)
Guerric de Streel, David Bol
Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology. ISLPED (2013)
David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat
7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. IEEE J. Solid State Circuits 48 (1) (2013)
Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat
An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT (2013)
David Bol, Cédric Hocquet, Francesco Regazzoni
CMOS Processes for Minimum Energy Under Timing Constraints. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. ISSCC (2012)
Julien De Vos, Denis Flandre, David Bol
Pushing Adaptive Voltage Scaling Fully on Chip. J. Low Power Electron. 8 (1) (2012)
Stéphanie Kerckhof, François Durvaux, Cédric Hocquet, David Bol, François-Xavier Standaert
Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint. CHES (2012)
Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren
Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation. RFIDSec (2011)
Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. J. Cryptogr. Eng. 1 (1) (2011)
David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. ISCAS (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

David Bol