Damien Croain

Publication Activity (10 Years)

Years Active: 2011-2017
Publications (10 Years): 5

Top Topics

Design Considerations

Silicon On Insulator

Random Access Memory

Top Venues

Publications

Kedar Janardan Dhori, Hitesh Chawla, Ashish Kumar, Prashant Pandey, Promod Kumar, Lorenzo Ciampolini, Florian Cacho, Damien Croain
High-yield design of high-density SRAM for low-voltage and low-leakage operations. DFT (2017)
Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, D. Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. VLSI Circuits (2016)
Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche
A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. ISCAS (2016)
Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC (2015)
Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC (2015)
N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
Bottom-up digital system-level reliability modeling. CICC (2011)
Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC (2011)