8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Sylvain ClercMehdi SaliganeFady AbouzeidMartin CochetJean-Marc DaveauCyril BottoniDavid BolJulien De VosDominique ZamoraBenjamin CoefficDimitri SoussanDamien CroainMehdi NaceurPierre SchambergerPhilippe RocheDennis SylvesterPublished in: ISSCC (2015)